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| M7040N 64K x 72-bit Entry NETWORK PACKET SEARCH ENGINE PRELIMINARY DATA FEATURES SUMMARY s 64K DATA ENTRIES IN 72-BIT MODE s Figure 1. 388-ball PBGA Package s TABLE MAY BE PARTITIONED INTO UP TO EIGHT (8) OCTANTS (Data entry width in each octant is configurable as 36, 72, 144, or 288 bits.) UP TO 100 MILLION SUSTAINED SEARCHES PER SECOND IN 72-BIT and 144-BIT CONFIGURATIONS UP TO 50 MILLION SEARCHES PER SECOND IN 36-BIT and 288-BIT CONFIGURATIONS SEARCHES ANY SUB-FIELD IN A SINGLE CYCLE OFFERS BIT-BY-BIT and GLOBAL MASKING SYNCHRONOUS, PIPELINED OPERATION UP TO 31 SEARCH ENGINES CASCADABLE WITHOUT PERFORMANCE DEGRADATION WHEN CASCADED, THE DATABASE ENTRIES CAN SCALE FROM 496K TO 3968K DEPENDING ON THE WIDTH OF THE ENTRY GLUELESS INTERFACE TO INDUSTRYSTANDARD SRAMS SIMPLE HARDWARE INSTRUCTION INTERFACE IEEE 1149.1 TEST ACCESS PORT OPERATING SUPPLY VOLTAGES INCLUDE: VDD (Operating Core Supply Voltage) = 1.5V for 66 and 83MSPS; 1.65V for 100MSPS VDDQ (Operating Supply Voltage for I/O) = 2.5 or 3.3V 388 PBGA, 35mm x 35mm 388-ball PBGA 35mm x 35mm s s s s s s s s s s s May 2002 1/159 M7040N TABLE OF CONTENTS DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Range (Table 1.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Switch/Router Implementation Using the M7040N (Figure 2.) . . . . . Signal Names (Table 2.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Connections (Figure 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . M7040N Block Diagram (Figure 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . ....... ....... ....... ....... ....... ....... ....... ....... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... .....7 .....7 .....7 .....7 .....7 .....8 .....9 . . . . 10 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Absolute Maximum Ratings (Table 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 DC and AC Measurement Conditions (Table 4.) . . . . . . . . . . . . . . . . M7040N 1.8, 2.5, or 3.3V AC Testing Load (Figure 5.) . . . . . . . . . . . M7040N 1.8, 2.5, or 3.3V Input Waveform (Figure 6.) . . . . . . . . . . . M7040N 1.8, 2.5, or 3.3V I/O Output Load Equivalent (Figure 7.) . . Capacitance (Table 5.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics (Table 6.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Timing Waveforms with CLK2X (Figure 8.) . . . . . . . . . . . . . . . . . AC Timing Waveforms with CLK1X (Figure 9.) . . . . . . . . . . . . . . . . . AC Timing Parameters with CLK2X (Table 7.) . . . . . . . . . . . . . . . . . AC Timing Parameters with CLK1X (Table 8.) . . . . . . . . . . . . . . . . . ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... . . . . 12 . . . . 13 . . . . 13 . . . . 13 . . . . 14 . . . . 14 . . . . 15 . . . . 16 . . . . 17 . . . . 18 OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Command Bus and DQ Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Database Entry (Data Array and Mask Array) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Arbitration Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Pipeline and SRAM Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Full Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Connection Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 CLOCKS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Clocks (CLK2X and PHS_L) (Figure 10.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Clocks (CLK1X) (Figure 11.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Clocks for All Timing Diagrams (Figure 12.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 PLL USAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2/159 M7040N REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Register Overview (Table 9.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Comparand Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Comparand Register Selection During SEARCH and LEARN Instructions (Figure 13.) . . . . . . . . . 23 Mask Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Addressing the Global Masks Register Array (Figure 14.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 SEARCH-Successful Registers (SSR[0:7]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 SEARCH-Successful Register (SSR) Description (Table 10.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 The Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Command Register Field Descriptions (Table 11.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 The Information Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Information Register Field Descriptions (Table 12.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 The Read Burst Address Register (RBURREG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Read Burst Register Description (Table 13.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 The Write Burst Address Register (WBURREG). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Write Burst Register Description (Table 14.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 The NFA Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 NFA Register (Table 15.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 SEARCH ENGINE ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Data and Mask Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 M7040N Database Width Configuration (Figure 15.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Bit Position Match (Table 16.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Multi-width Configuration Example (Figure 16.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 M7040N Data and Mask Array Addressing (Figure 17.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 COMMAND CODES AND PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Command Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Commands and Command Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Command Codes (Table 17.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Command Parameters (Table 18.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 READ COMMAND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Single Location READ Cycle Timing (Figure 18.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Burst READ of the Data and Mask Arrays (BLEN = 4) (Figure 19.) . . . . . . . . . . . . . . . . . . . . . . . . 33 READ Command Parameters (Table 19.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Data and Mask Array, SRAM Read Address Format (Table 20.) . . . . . . . . . . . . . . . . . . . . . . . . . . 34 READ Address Format for Internal Registers (Table 21.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 READ Address Format for Data and Mask Arrays (Table 22.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 3/159 M7040N WRITE COMMAND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Single Location WRITE Cycle Timing (Figure 20.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Burst WRITE of the Data and Mask Arrays (BLEN = 4) (Figure 21.). . . . . . . . . . . . . . . . . . . . . . . . 37 (Single) WRITE Address Format for Data and Mask Arrays or SRAM (Table 23.) . . . . . . . . . . . . . 37 WRITE Address Format for Internal Registers (Table 24.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 WRITE Address Format for Data and Mask Array (Burst Write) (Table 25.) . . . . . . . . . . . . . . . . . . 38 Parallel WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 SEARCH COMMAND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 72-bit Configuration with Single Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hardware Diagram for a Table with One Device (Figure 22.) . . . . . . . . . . . . . . . . . . . 72-Bit Configuration SEARCH Timing Diagram for One Device (Figure 23.) . . . . . . . x72 Table with One Device (Figure 24.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Latency of SEARCH from Instruction to SRAM Access Cycle, 72-bit (Table 26.) . . . . Shift of SSF and SSV from SADR (Table 27.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...... ...... ...... ...... ...... ...... . . . . 38 . . . . 39 . . . . 40 . . . . 41 . . . . 41 . . . . 41 . . . . 42 . . . . 43 . . . . 43 . . . . 44 . . . . 45 . . . . 48 . . . . 48 72-bit SEARCH on Tables Configured as x72 Using up to Eight M7040N Devices . . . . . Hit/Miss Assumption (Table 28.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hardware Diagram for a Table with Eight Devices (Figure 25.) . . . . . . . . . . . . . . . . . . . . . . . x72 Table with Eight Devices (Figure 26.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Diagrams for x72 Using up to Eight M7040N Devices. . . . . . . . . . . . . . . . . . . . . . . . . Latency of SEARCH from Instruction to SRAM Access Cycle (Table 29.) . . . . . . . . . . . . . . . Shift of SSF and SSV from SADR (Table 30.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72-bit Search on Tables Configured as x72 Using Up To 31 M7040N Devices . . . . . . . . . . . . 48 Hit/Miss Assumption (Table 31.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Hardware Diagram for a Table with 31 Devices (Figure 30.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Hardware Diagram for a Block of Up To Eight Devices (Figure 31.) . . . . . . . . . . . . . . . . . . . . . . . . 51 x72 Table with 31 Devices (Figure 32.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Timing Diagrams for x72 Using Up To 31 M7040N Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Latency of SEARCH from Instruction to SRAM Access Cycle (Table 32.) . . . . . . . . . . . . . . . . . . . 64 Shift of SSF and SSV from SADR (Table 33.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 144-bit Configuration with Single Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hardware Diagram for a Table with 1 Device (Figure 44.) . . . . . . . . . . . . . . . . . . . . . Timing Diagram for a 144-bit SEARCH for 1 Device (Figure 45.) . . . . . . . . . . . . . . . . x144 Table with One Device (Figure 46.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Latency of SEARCH from Instruction to SRAM Access Cycle, 144-bit (Table 34.). . . Shift of SSF and SSV from SADR (Table 35.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...... ...... ...... ...... ...... ...... . . . . 64 . . . . 65 . . . . 66 . . . . 67 . . . . 67 . . . . 67 144-bit Search on Tables Configured as x144 Using Up to Eight M7040N Devices . . . . . . . . 68 Hit/Miss Assumption (Table 36.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Hardware Diagram for a Table with Eight Devices (Figure 47.) . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 x144 Table with Eight Devices (Figure 48.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Timing Diagrams for x144 Using Up to Eight M7040N Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Latency of SEARCH from Instruction to SRAM Access Cycle, 144-bit (Table 37.). . . . . . . . . . . . . 74 Shift of SSF and SSV from SADR (Table 38.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 4/159 M7040N 144-bit Search on Tables Configured as x144 Using Up to 31 M7040N Devices. . . . . . . . . . . 74 Hit/Miss Assumption (Table 39.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Hardware Diagram for a Table with 31 Devices (Figure 52.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Hardware Diagram for a Block of Up to Eight Devices (Figure 53.) . . . . . . . . . . . . . . . . . . . . . . . . 77 x144 Table with 31 Devices (Figure 54.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Timing Diagrams for x144 Using Up to 31 M7040N Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Latency of SEARCH from Instruction to SRAM Access Cycle, 144-bit (Table 40.). . . . . . . . . . . . . 90 Shift of SSF and SSV from SADR (Table 41.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 288-bit SEARCH on Tables Configured as x288 Using a Single M7040N Device . . . . . . . . . . 90 Hardware Diagram for a Table with One Device (Figure 66.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Timing Diagram for 288-bit SEARCH (One Device) (Figure 67.) . . . . . . . . . . . . . . . . . . . . . . . . . . 92 x288 Table with One Device (Figure 68.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Latency of SEARCH from Cycles C and D to SRAM Access Cycle (Table 42.) . . . . . . . . . . . . . . . 93 Shift of SSF and SSV from SADR (Table 43.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 288-bit SEARCH on Tables x288-configured Using Up to Eight M7040N Devices . . . . . . . . . 94 Hit/Miss Assumption (Table 44.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Hardware Diagram for a Table with Eight Devices (Figure 69.) . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 x288 Table with Eight Devices (Figure 70.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Timing Diagrams for x288-configured Using Up to Eight M7040N Devices . . . . . . . . . . . . . . . . . . 98 Latency of SEARCH from Cycles C and D to SRAM Access Cycle, 288-bit (Table 45.). . . . . . . . 101 Shift of SSF and SSV from SADR (Table 46.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 288-bit Search on Tables Configured as x288 Using Up to 31 M7040N Devices. . . . . . . . . . 101 Hit/Miss Assumption (Table 47.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Hardware Diagram for a Table with 31 Devices (Figure 74.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Hardware Diagram for a Block of Up to Eight Devices (Figure 75.) . . . . . . . . . . . . . . . . . . . . . . . 104 x288 Table with 31 Devices (Figure 76.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Timing Diagrams for x288 Using Up to 31 M7040N Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Latency of SEARCH from Cycles C and D to SRAM Access Cycle, 288-bit (Table 48.). . . . . . . . 117 Shift of SSF and SSV from SADR (Table 49.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 MIXED SEARCHES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Tables Configured with Different Widths Using an M7040N with CFG_L LOW . . . . . . . . . . . . . . 117 Tables Configured to Different Widths using an M7040N with CFG_L HIGH . . . . . . . . . . . . . . . . 117 Timing Diagram for Mixed SEARCH (One Device) (Figure 88.) . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Multi-Width Configurations Example (Figure 89.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Searches with CFG_L Set HIGH (Table 50.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 LRAM AND LDEV DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 LEARN COMMAND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Timing Diagram of LEARN: TLSZ = 00 (Figure 90.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing Diagram of LEARN: TLSZ = 01 (Except on the Last Device) (Figure 91.). . . . . . . . . . Timing Diagram of LEARN on Device 7: TLSZ = 01 (Figure 92.) . . . . . . . . . . . . . . . . . . . . . . Latency of SRAM WRITE Cycle from Second Cycle of LEARN Instruction (Table 51.) . . . . . . . . 121 . . . 122 . . . 123 . . . 123 5/159 M7040N DEPTH-CASCADING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Depth-Cascading Up to Eight Devices (One Block) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Depth-Cascading Up to 31 Devices (4 Blocks) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Depth-Cascading to Generate a "FULL" Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Depth-Cascading to Form a Single Block (Figure 93.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Depth-Cascading Four Blocks (Figure 94.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 "FULL" Generation in a Cascaded Table (Figure 95.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 SRAM ADDRESSING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 Generating an SRAM Bus Address (Table 52.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 SRAM PIO Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 SRAM READ with a Table of One Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 SRAM READ Access for One Device (Figure 96.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 SRAM READ with a Table of Up to Eight Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 Table with Eight Devices (Figure 97.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 SRAM READ Through Device 0 in a Block of Eight Devices (Figure 98.). . . . . . . . . . . . . . . . . . . 132 SRAM READ Timing for Device 7 in a Block of Eight Devices (Figure 99.) . . . . . . . . . . . . . . . . . 133 SRAM READ with a Table of Up to 31 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table of 31 Devices Made of Four Blocks (Figure 100.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SRAM READ Through Device 0 in a Bank of 31 Devices (Device 0 Timing) (Figure 101.) . . SRAM READ Through Device 0 in a Bank of 31 Devices (Device 30 Timing) (Figure 102.) . . . . 134 . . . 135 . . . 136 . . . 137 SRAM WRITE with a Table of One Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 SRAM WRITE Access for One Device (Figure 103.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 SRAM WRITE with a Table of Up to Eight Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Table with Eight Devices (Figure 104.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 SRAM WRITE Through Device 0 in a Block of Eight Devices (Figure 105.) . . . . . . . . . . . . . . . . . 142 SRAM WRITE Timing for Device 7 in a Block of Eight Devices (Figure 106.). . . . . . . . . . . . . . . . 143 SRAM WRITE with Table(s) of Up to 31 Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table of 31 Devices (Four Blocks) (Figure 107.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SRAM WRITE Through Device 0 in a Bank of 31 Devices (Device 0 Timing) (Figure 108.). . SRAM WRITE Through Device 0 in a Bank of 31 Devices (Device 30 Timing) (Figure 109.). . . . 144 . . . 145 . . . 146 . . . 147 JTAG (1149.1) TESTING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Supported Operations (Table 53.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 TAP Device ID Register (Table 54.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 APPENDIX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 6/159 M7040N DESCRIPTION Overview ST Microelectronics, Inc.'s M7040N Search Engine incorporates patent-pending Associative Processing TechnologyTM (APT) and is designed to be a high-performance, pipelined, synchronous, 64K-entry network database search engine. The M7040N database entry size can be 72 bits, 144 bits, or 288 bits. In the 72-bit entry mode, the size of the database is 64K entries. In the 144-bit mode, the size of the database is 32K entries, and in the 288-bit mode, the size of the database is 16K entries. The M7040N is configurable to support multiple databases with different entry sizes. The 36-bit entry table can be implemented using the Global Mask Registers (GMRs) building-database size of 128K entries with a single device. Performance The Search Engine can sustain 100 million transactions per second when the database is programmed or configured as 72 or 144 bits. When the database is programmed to have an entry size Table 1. Product Range Part Number M7040N-100ZA1 M7040N-083ZA1 M7040N-066ZA1 Operating Supply Voltage 1.65V 1.5V 1.5V Operating I/O Voltage 2.5 or 3.3V 2.5 or 3.3V 2.5 or 3.3V Speed 100MHz 83MHz 66MHz Temperature Range Commercial Commercial Commercial of 36 or 288 bits, the Search Engine will perform at 50 million transactions per second. STM's M7040N can be used to accelerate network protocols such as Longest-prefix Match (CIDR), ARP, MPLS, and other Layer 2, 3, and 4 protocols. Applications This high-speed, high-capacity Search Engine can be deployed in a variety of networking and communications applications. The performance and features of the M7040N make it attractive in applications such as Enterprise LAN switches and routers and broadband switching and/or routing equipment supporting multiple data rates at OC- 48 and beyond. The Search Engine is designed to be scalable in order to support network database sizes to 3968K entries specifically for environments that require large network policy databases. Figure 4, page 10 shows the block diagram for the M7040N device. Figure 2. Switch/Router Implementation Using the M7040N Sys tem Bus m Progra ry Memo Host ASIC Switch Fabric h Searc e Engin SRAM Bank Ne two rk L ine Inte Switch or rocess P rfac es AI04272 7/159 M7040N Table 2. Signal Names Symbol Type(1) Description SADR[23:0] CE_L WE_L OE_L ALE_L SRAM Interface T T T T T SRAM Address SRAM Chip Enable SRAM Write Enable SRAM Output Enable Address Latch Enable Clocks and Reset CLK_MODE CLK2X_CLK1X PHS_L TEST_CO(2) TEST TEST_FM RST_L TEST_PB(3) CFG_L I I I I I I I I I Clock Mode Master Clock Phase Test Output (ST Use Only) Test Input (ST Use Only) Test Input (ST Use Only) Reset Test Input (ST Use Only) Cascade Interface LHI[6:0] LHO[1:0] BHI[2:0] BHO[2:0] I O I O I O O Local Hit In Local Hit Out Block Hit In Block Hit Out Full In Full Out Full Flag Configuration FULI[6:0] FULO[1:0] FULL Command and DQ Bus CMD[10:0] CMDV DQ[71:0] ACK(4) EOT SSF SSV MULTI_HIT HIGH_SPEED CLKTUNE[3:0] (4) I I I/O T T T T O I I Command Bus Command Valid Address/Data Bus READ Acknowledge End of Transfer SEARCH Successful Flag SEARCH Successful Flag Valid Multiple Hit Flag 100MHz Indicator PLL Tuner Device Identification ID[4:0] I Device Identification Supplies VDD n/a Chip Core Supply (1.5V for 66 and 83MSPS; 1.65 for 100MSPS) Chip I/O Supply (2.5 or 3.3V) VDDQ n/a Test Access Port TDI TCK TDO TMS TRST_L I I T I I Test Access Port's Test Data In Test Access Port's Test Clock Test Access Port's Test Data Out Test Access Port's Test Mode Select Test Access Port's Reset Note: 1. Signal types are: I = Input only; I/O = Input or Output; O = Output; and T = Tristate See DESCRIPTIONS FOR CONNECTION DIAGRAM (Figure 3, page 9), page 152 for individual connection details. 2. In the previous versions of this specification, this signal was called, "CLK_OUT." 3. In previous versions of this specification, this signal was called, "PLL_BYPASS." 4. ACK and EOT Signals require a weak, external pull-down resistor of 47 K or 100 K. 8/159 M7040N Figure 3. Connections 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF 2 3 4 DQ67 5 DQ63 6 VDDQ 7 DQ57 8 DQ53 9 DQ51 10 DQ43 11 DQ41 12 DQ37 13 DQ35 14 DQ31 15 VDDQ 16 DQ25 17 DQ21 18 DQ17 19 VDDQ 20 DQ9 21 DQ5 22 DQ3 23 24 25 26 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF CLK DQ71 VDDQ TUNE3 VSS TEST_ V HIGH_ CLK DDQ SPEED TUNE0 FM TEST_ CFG_L PB VDD VDD VSS SADR 0 TDI DQ69 DQ65 DQ61 DQ59 DQ55 VDDQ DQ47 DQ45 DQ39 VDDQ DQ33 DQ29 DQ27 DQ23 VDDQ DQ15 DQ11 DQ7 VDDQ VDD DQ1 TCK TRST_ L ID0 TMS VDD VDD VSS VDD VDD VSS VDD NC8 DQ49 VDDQ VSS VDD VDD VDD VDD VDD VDD VDD DQ19 DQ13 NC7 VDD VDD SADR V DDQ 1 SADR 3 SADR 5 SADR 2 SADR 4 TDO VDD VSS VSS VSS VSS VDD VDD VDD VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VDD VDDQ VDD VSS VDD VDD ID1 ID2 VDD VSS VSS SADR V DDQ 6 SADR SADR 8 7 VDDQ SADR 9 ID3 ID4 VDD VSS VSS VSS VSS VDD LHI0 LHI1 NC1 VSS VSS NC6 LHI2 LHI3 VDDQ SADR SADR SADR 11 12 10 SADR SADR V DDQ 14 13 VDD SADR 15 SADR 16 LHI6 LHI4 LHI5 VSS VSS LHO0 LHO1 VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD VDDQ BHI0 VDD VDD VDD VDD VDDQ SADR 17 SADR SADR 18 19 SADR SADR 21 20 SADR V DDQ 22 CLK_ SADR MODE 23 BHI1 BHI2 VDD VDD VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDD VDD MULTI_ V BHO0 DD HIT VDDQ BHO1 VDD VDD VSS VSS VSS VSS VSS VSS VSS VDD VDD VDD VDD VDD BHO2 VSS VDD VDD VSS VSS VSS VSS VSS VSS VDD VDD FULI0 VDDQ FULI1 VSS CLK1x/ OE_L PHS_L CLK2x CE_L VDDQ WE_L FULI2 FULI3 FULI4 VSS VSS VDDQ FULI5 NC2 VSS VSS VSS NC5 CMDV ALE_L FULI6 FULO0 VDD VSS VDD CMD1 CMD0 FULO1 VDDQ VDD VSS VSS VDD CMD3 CMD2 FULL ACK VDD VSS VSS VDD CMD5 CMD4 VSS EOT VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VSS VDDQ VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS VSS VSS VSS VDD VSS VDD VSS VSS VDD CMD6 VDDQ RST_L VDDQ VDD NC3 DQ46 VDD VDD VDDQ VDD DQ20 DQ16 NC4 VDD VDD VDD VDDQ CMD8 CMD7 CLK TUNE1 TEST VSS DQ70 VDDQ DQ64 DQ60 DQ58 DQ54 DQ50 DQ44 DQ42 DQ38 DQ32 DQ28 DQ26 VDDQ DQ18 DQ12 DQ10 DQ6 VDDQ DQ0 VSS TEST_ CLK DQ68 CO TUNE2 DQ66 DQ62 VDDQ DQ56 DQ52 DQ48 VDDQ DQ40 DQ36 DQ34 DQ30 VDDQ DQ24 DQ22 DQ14 VDDQ DQ8 DQ4 DQ2 SSV SSF CMD10 CMD9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 AI04646 9/159 M7040N Figure 4. M7040N Block Diagram PHS_L CLK1X_CLK2X RST_L CLK_MODE Comparand Registers[15:0] Global Mask Registers [15:0] Information and Command Register Burst Read Register Burst Write Register Next Free Address Register Search Successful Index Registers [7:0] (All registers are 72-bit-wide) TAP Controller TAP DQ [71:0] Compare/PIO Data Cmd Compare/PIO Data Address Decode CMD [10:0] CMDV ACK EOT Priority Encode Match Logic Command Decode and PIO Access Configurable as 128K x 36 64K x 72 32K x 144 16K x 288 Data Array Configurable as 128K x 36 64K x 72 32K x 144 16K x 288 Mask Array SADR [23:0] Pipeline and SRAM Control OE_L WE_L CE_L ALE_L ID [4:0] FULL [6:0] Full Logic FULL LHI [6:0] BHI [2:0] Arbitration Logic FULO [1:0] LHO [1:0] BHO [2:0] SSF SSV AI04645 10/159 M7040N MAXIMUM RATING Stressing the device above the rating listed in the "Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is Table 3. Absolute Maximum Ratings Symbol TSTG TSLD(1) VDD VDDQ VDDQ VDDQ IO Parameter Storage Temperature (VDD Off) Lead Solder Temperature for 10 seconds CLK1X = 83MHz VDD Operating Supply Voltage VDDQ Voltage for I/O (3.3V) VDDQ Voltage for I/O (2.5V) VDDQ Voltage for I/O (1.8V) Output Current CLK1X = 100MHz Value -0 to 70 235 1.575 1.733 3.5 2.625 1.9 100 Unit C C V V V V V mA not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Note: 1. Soldering temperature not to exceed 260C for 10 seconds (total thermal budget not to exceed 150C for longer than 30 seconds). 11/159 M7040N DC AND AC PARAMETERS This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived from tests performed under the MeasureTable 4. DC and AC Measurement Conditions Sym VDD Parameter VDD Operating Supply Voltage CLK1X = 83MHz CLK1X = 100MHz Min 1.425 1.568 3.1 2.375 1.7 0 -5 Max 1.575 1.733 3.5 2.625 1.9 70 +5 GND to 3.0 GND to 2.5 GND to 1.8 2ns (see Figure 6, page 13) 2ns (see Figure 6, page 13) 1.5 1.25 0.9 1.5 1.25 0.9 (see Figure 5 and Figure 7, page 13) Units V V V V V C % V V V ns ns V V V V V V V ment Conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. VDDQ VDDQ Voltage for I/O (3.3V) VDDQ VDDQ Voltage for I/O (2.5V) VDDQ VDDQ Voltage for I/O (1.8V) tA Ambient Operating Temperature Supply Voltage Tolerance Input Pulse Levels (VDDQ = 3.3V) Input Pulse Levels (VDDQ = 2.5V) Input Pulse Levels (VDDQ = 1.8V) Input Rise and Fall Times at 0.3V and 2.7V (VDDQ = 3.3V) Input Rise and Fall Times at 0.25V and 2.25V (VDDQ = 2.5V) Input Timing Reference Levels (VDDQ = 3.3V) Input Timing Reference Levels (VDDQ = 2.5V) Input Timing Reference Levels (VDDQ = 1.8V) Output Timing Reference Levels (VDDQ = 3.3V) Output Timing Reference Levels (VDDQ = 2.5V) Output Timing Reference Levels (VDDQ = 1.8V) Output Load Note: 1. Maximum allowable applies to overshoot only (VDDQ is 3.3V supply). 2. Minimum allowable applies to undershoot only. 12/159 M7040N Figure 5. M7040N 1.8, 2.5, or 3.3V AC Testing Load Z0 = 50 DOUT CL 50 VL = 1.25V for VDDQ = 2.5V VL = 1.50V for VDDQ = 3.3V AI04751 Figure 6. M7040N 1.8, 2.5, or 3.3V Input Waveform +2.5V VDDQ = 2.5V / +3.0V VDDQ = 3.3V 90% 90% 10% GND 10% AI04752 Figure 7. M7040N 1.8, 2.5, or 3.3V I/O Output Load Equivalent VDDQ 208 for VDDQ = 2.5V 158 for VDDQ = 3.3V Q 192 for VDDQ = 2.5V 175 for VDDQ = 3.3V 5pF For Hi-Z and VOL/VOH(1, 2) AI04753 Note: 1. Output loading is specified with CL = 5pF as in Figure 7. Transition is measured at 200 mV from steady-state voltage. 2. The load used for VOH, VOL testing is shown in Figure 7. 13/159 M7040N Table 5. Capacitance Symbol CIN CIO(3) Parameter Input Capacitance Output Capacitance Test Condition(1,2) VIN = 0V VOUT = 0V Min Max 6 6 Unit pF pF Note: 1. Effective capacitance measured with power supply. Sampled only, not 100% tested. 2. At 25C, f = 1MHz. 3. Outputs deselected. Table 6. DC Characteristics Sym ILI ILO VIL VIH VIL VIH VIL VIH Parameter Input Leakage Current Output Leakage Current Input Low Voltage (VDDQ = 3.3V) Input High Voltage (VDDQ = 3.3V) Input Low Voltage (VDDQ = 2.5V) Input High Voltage (VDDQ = 2.5V) Input Low Voltage (VDDQ = 1.8V) Input High Voltage (VDDQ = 1.8V) VDDQ = VDDQ(min), IOL = 16mA VDDQ = VDDQ(min), IOH = 8mA VDDQ = VDDQ(min), IOL = 8mA VDDQ = VDDQ(min), IOH = 8mA VDDQ = VDDQ(min), IOL = 8mA VDDQ = VDDQ(min), IOH = 8mA 100MHz Search Rate 83MHz Search Rate 66MHz Search Rate 100MHz Search Rate, IOUT = 0mA IDD2 3.3V Supply Current at VDD(max) 83MHz Search Rate, IOUT = 0mA 66MHz Search Rate, IOUT = 0mA 100MHz Search Rate, IOUT = 0mA IDD2 2.5V Supply Current at VDD(max) 83MHz Search Rate, IOUT = 0mA 66MHz Search Rate, IOUT = 0mA Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70C; VDD = 1.5V. Test Condition(1) VDDQ = VDDQ(max), VIN = 0 to VDDQ(max) VDDQ = VDDQ(max), VIN = 0 to VDDQ(max) Min -10 -10 -0.3 2.0 -0.3 1.7 -0.3 Max +10 +10 0.8 VDDQ + 0.3 0.7 VDDQ + 0.3 0.35 * VDDQ Unit A A V V V V V V V V 0.7 * VDDQ VDDQ + 0.3 0.4 2.4 0.4 2.0 0.45 VDD - 0.45 6.0 5.0 4.0 350 300 240 350 300 240 VOL Output Low Voltage (VDDQ = 3.3V) VOH Output High Voltage (VDDQ = 3.3V) VOL Output Low Voltage (VDDQ = 2.5V) VOH Output High Voltage (VDDQ = 2.5V) VOL Output Low Voltage (VDDQ = 1.8V) VOH Output High Voltage (VDDQ = 1.8V) 1.65V Supply Current at VDD(max) IDD1 1.5V Supply Current at VDD(max) 1.5V Supply Current at VDD(max) V V V V A A A mA mA mA mA mA mA 14/159 M7040N Figure 8. AC Timing Waveforms with CLK2X Cycle Cycle Cycle Cycle Cycle Cycle Cycle Cycle Cycle Cycle Cycle Cycle Cycle 2 4 6 8 10 12 0 1 3 5 7 9 11 CLK2X CLK tIHCH tISCH Signal Group 0 tISCH tISCH tIHCH Signal Group 1 tIHCH tIHCH tICHCH Signal Group 2 tICSCH tCKHOV Signal Group 3 tCKHOV tCKHSHZ Signal Group 4 tCKHSV tCKHSLZ tCKHDZ Signal Group 5 tCKHDV Signal Group 0: PHS_L, RST_L Signal Group 1: DQ, CMD, CMDV Signal Group 2: LHI, BHI, FULI Signal Group 3: LHO, BHO, FULO, FULL Signal Group 4: SADR, CE_L, OE_L, WE_L, ALE_L, SSF, SSV Signal Group 5: DQ, ACK, EOT AI04748 15/159 M7040N Figure 9. AC Timing Waveforms with CLK1X Cycle Cycle Cycle Cycle Cycle Cycle Cycle Cycle Cycle Cycle Cycle Cycle Cycle 2 4 6 8 10 12 0 1 3 5 7 9 11 CLK1X CLK tIHCH tISCH Signal Group 0 tISCH tISCH Signal Group 1 tIHCH tIHCH tICHCH Signal Group 2 tICSCH tCKHOV Signal Group 3 tCKHOV tCKHSHZ Signal Group 4 tCKHSV tCKHSLZ tCKHDZ Signal Group 5 tCKHDV Signal Group 0: PHS_L, RST_L Signal Group 1: DQ, CMD, CMDV Signal Group 2: LHI, BHI, FULI Signal Group 3: LHO, BHO, FULO, FULL Signal Group 4: SADR, CE_L, OE_L, WE_L, ALE_L, SSF, SSV Signal Group 5: DQ, ACK, EOT AI04749 16/159 M7040N Table 7. AC Timing Parameters with CLK2X M7040N066 Row Sym (VDDQ = 3.3V, 2.5V) Min 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Note: 1. 2. 3. 4. M7040N083 (VDDQ = 3.3V, 2.5V, 1.8V) Min 40 Max 166 0.5 2.4 2.4 1.8 0.6 3.5 0.6 M7040N100 (VDDQ = 3.3V, 2.5V) Min 40 Max 200 0.5 2.0 2.0 1.5 0.5 3.0 0.5 MHz CLK2X frequency ms ns ns ns ns ns ns 6.5 7.0 6.5 7.0 5.5 6.0 ns ns ns ns ns ns PLL lock time CLK2X high pulse(2) CLK2X low pulse(2) Input Setup Time to CLK2X rising edge(2) Input Hold Time to CLK2X rising edge(2) Cascaded Input Setup Time to CLK2X rising edge(2) Cascaded Input Hold Time to CLK2X rising edge(2) Rising edge of CLK2X to LHO, FULO, BHO, FULL valid(3) Rising edge of CLK2X to DQ valid(3) Rising edge of CLK2X to DQ high-Z(4) Rising edge of CLK2X to SRAM bus valid(3) Rising edge of CLK2X to SRAM bus high-Z(4) Rising edge of CLK2X to SRAM bus low-Z(4) Unit Description(1) Max 133 0.5 fCLOCK tCLOK tCKHI tCKLO tISCH tIHCH tICSCH tICHCH tCKHOV tCKHDV tCKHDZ tCKHSV tCKHSHZ tCKHSLZ 40 3.0 3.0 2.5 0.6 4.2 0.6 8.5 9.0 8.5 9.0 6.5 7.0 7.0 7.5 7.0 7.5 6.0 6.5 Valid for Ambient Operating Temperature: TA = 0 to 70C; VDD = 1.5V. Values are based on 50% signal levels. Based on an AC load of CL = 30pF (see Figure 5, Figure 6, and Figure 7, page 13). These parameters are sampled and not 100% tested, and are based on an AC load of 5pF. 17/159 M7040N Table 8. AC Timing Parameters with CLK1X M7040N066 Row Sym (VDDQ = 3.3V, 2.5V, 1.8V) Min 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Note: 1. 2. 3. 4. M7040N083 (VDDQ = 3.3V, 2.5V, 1.8V) Min 20 Max 83 0.5 5.4 5.4 1.8 0.6 3.5 0.5 M7040N100 (VDDQ = 3.3V, 2.5V) Min 20 Max 100 0.5 4.5 4.5 1.5 0.5 3.0 0.5 MHz CLK1X frequency ms ns ns ns ns ns ns 6.5 7.0 6.5 7.0 5.5 6.0 ns ns ns ns ns ns PLL lock time CLK1X high pulse(2) CLK1X low pulse(2) Input Setup Time to CLK1X edge(2) Input Hold Time to CLK1X edge(2) Cascaded Input Setup Time to CLK1X rising edge(2) Cascaded Input Hold Time to CLK1X rising edge(2) Rising edge of CLK1X to LHO, FULO, BHO, FULL valid(3) Rising edge of CLK1X to DQ valid(3) Rising edge of CLK1X to DQ high-Z(4) Rising edge of CLK1X to SRAM bus valid(3) Rising edge of CLK1X to SRAM bus high-Z(4) Rising edge of CLK1X to SRAM bus low-Z(4) Unit Description(1) Max 66 0.5 fCLOCK tCLOK tCKHI tCKLO tISCH tIHCH tICSCH tICHCH tCKHOV tCKHDV tCKHDZ tCKHSV tCKHSHZ tCKHSLZ 20 6.75 6.75 2.5 0.6 4.2 0.6 8.5 9.0 8.5 9.0 6.5 7.0 7.0 7.5 7.0 7.5 6.0 6.5 Valid for Ambient Operating Temperature: TA = 0 to 70C; VDD = 1.5V. Values are based on 50% signal levels and a 50/50% duty cycle of CLK1X. Based on an AC load of CL = 30pF (see Figure 5, Figure 6, and Figure 7, page 13). These parameters are sampled and not 100% tested, and are based on an AC load of 5pF. 18/159 M7040N OPERATION Command Bus and DQ Bus CMD[10:0] carries the command and its associated parameter. DQ[71:0] is used for data transfer to and from the database entries. These entries comprise a data and a mask field that are organized as data and mask arrays. The DQ Bus carries the search data (of the data and mask arrays and internal registers) during the SEARCH command as well as the address and data during READ and/or WRITE operations. The DQ Bus can also carry the address information for the flow-through accesses to the external SRAMs and/or SSRAMs. Database Entry (Data Array and Mask Array) Each database entry comprises a data and a mask field. The resultant value of the entry is "1," "0," or "X (don't care)," depending on the value in the data and mask bits. The on-chip priority encoder selects the first matching entry in the database that is nearest to location "0." Arbitration Logic When multiple Search Engines are cascaded to create large databases, the data being searched is presented to all Search Engines simultaneously in the cascaded system. If multiple matches occur within the cascaded devices, arbitration logic on the Search Engines will enable the winning device (with a matching entry that is closest to address "0" of the cascaded database) to drive the SRAM bus. Pipeline and SRAM Control Pipeline latency is added to give enough time to a cascaded system's arbitration logic to determine the device that will drive the index of the matching entry on the SRAM bus. Pipeline logic adds latency to both the SRAM access cycles and the SSF and SSV signals to align them to the host ASIC receiving the associated data. Full Logic Bit[0] in each of the 72-bit entries has a special purpose for the LEARN command (0 = empty, 1 = full). When all the data entries have bit[0] = 1, the database asserts the FULL Flag, indicating all the Search Engines in the depth-cascaded array are full. Connection Descriptions CLOCK MODE (CLK_MODE). This signal allows the selection of clock input to the CLK1X/CLK2X pin. If the CLK_MODE pin is low, CLK2X must be supplied on that pin. PHS_L must also be sup- plied. If the CLK_MODE pin is high, CLK1X must be supplied on the CLK2X/CLK1X pin, and the PHS_L signal is not required. When the CLK_MODE is high, PHS_L is unused and should be externally grounded. Master Clock (CLK2X/CLK1X). Depending on the CLK_MODE pin, either the CLK2X or the CLK1X must be supplied. M7040N samples control and data signals on both the edges of CLK1X if CLK1X is supplied. M7040N samples all the data and control pins on the positive edge of CLK2X if the CLK2X and PHS_L signals are supplied. All signals are driven out of the device on the rising edge of CLK1X if CLK1X is supplied, and are driven on the rising edge of CLK2X (when PHS_L is low) if CLK2X is supplied. Phase (PHS_L). This signal runs at half the frequency of CLK2X and generates an internal clock from CLK2X (see Figure 10, page 21). Test Output (TEST_CO). This is test output and will stay unconnected in the application of the device. Test Input (TEST). This signal should be connected to ground. Test Input (TEST_FM). This signal should be connected to ground. Reset (RST_L). Driving RST_L low initializes the device to a known state. Test Input (TEST_PB). This signal should be connected to ground. Configuration. When CFG_L is low, M7040N will operate in backward compatibility mode with M7010 and M7020. When CFG_L is low, the CMD[10:9] should be externally grounded. With CFG_L low, the device will behave identically with M7010 and M7020, and the new feature added to M7040N will be disabled. When CFG_L is high, the additional command CMD[10:9] can be used and the following additional features will be supported: 1. 16 pairs of Global Masks are supported instead of eight; 2. Parallel WRITE to the data and mask arrays is supported (see Parallel WRITE, page 38); and 3. configuring tables of up to three different widths does not require table identification bits in the data array, thus saving two bits from each 72-bit 19/159 M7040N Command Bus (CMD[10:0]. [1:0] specifies the command; [10:2] contains the command parameters. The descriptions of individual commands explains the details of the parameters. The encoding of commands based on the [1:0] field are: - 00: PIO READ - 01: PIO WRITE - 10: SEARCH - 11: LEARN Command Valid (CMDV). Qualifies the CMD bus as follows: - 0: No Command - 1: Command Address/Data Bus (DQ[71:0]). Carries the Read and WRITE address as well as the data during register, data, and mask array operations. It carries the compare data during search operations. It also carries the SRAM address during SRAM PIO accesses. READ Acknowledge (ACK). Indicates that valid data is available on the DQ Bus during register, data, and mask array READ operations, or the data is available on the SRAM data bus during SRAM READ operations. Note: ACK Signals require a weak external pulldown resistor such as 47 or 100 K. End of Transfer (EOT). Indicates the end of burst transfer during READ or WRITE burst operations. Note: EOT Signals require a weak external pulldown resistor such as 47 K or 100 K. SEARCH Successful Flag (SSF). When asserted, this signal indicates that the device is the global winner in a SEARCH operation. SEARCH Successful Flag Valid (SSV). When asserted, this signal qualifies the SSF signal. Multiple Hit Flag (MULTI_HIT). When asserted, this signal indicates that there is more than one location having a match on this device. High Speed (HIGH_SPEED). When this signal is high, the device will run up to 100MHz and perform 100 million searches per second. However, in this mode, a TLSZ value of '00' is not supported in a system of a single device. Furthermore, the device will only support a TLSZ of '00' and '01' if more than one device is cascaded to form database tables. Clock Tune [3:0] (CLK_TUNE[3:0]). These test pins should be set to logic level 1001. SRAM Address (SADR[23:0]). This bus contains address lines to access off-chip SRAMs that contain associative data. See Table 52, page 128 for the details of the generated SRAM address. In a database of multiple M7040Ns, each corresponding bit of SADR from all cascaded devices must be connected. SRAM Chip Enable (CE_L). This is Chip Enable control for external SRAMs. In a database of multiple M7040Ns, CE_L of all cascaded devices must be connected. This signal is then driven by only one of the devices. SRAM Write Enable (WE_L). This is Write Enable control for external SRAMs. In a database of multiple M7040Ns, WE_L of all cascaded devices must be connected together. This signal is then driven by only one of the devices. SRAM Output Enable (OE_L). This is Output Enable control for external SRAMs. Only the last device drives this signal (with the LRAM bit set). Address Latch Enable (ALE_L). When this signal is low, the addresses are valid on the SRAM Address Bus. In a database of multiple M7040Ns, the ALE_L of all cascaded devices must be connected. This signal is then driven by only one of the devices. Local Hit In (LHI[6:0]). These pins depth-cascade the device to form a larger table size. One signal of this bus is connected to the LHO[1] or LHO[0] of each of the upstream devices in a block. Connect all unused LHI pins to a logic '0.' (For more information, see DEPTH-CASCADING, page 124.) Local Hit Out (LHO[1:0]). LHO[1] and LHO[0] are the same logical signal. LHO[1] or LHO[0] is connected to one input of the LHI bus of up to four downstream devices (in a block that contains up to eight devices). (For more information, see DEPTH-CASCADING, page 124.) Block Hit In (BHI[2:0]). Inputs from the previous BHO[2:0] are tied to the BHI[2:0] of the current device (see DEPTH-CASCADING, page 124). In a four-block system, the last block can contain only seven devices because the ID code 11111 is used for broadcast access. Block Hit Out (BHO[2:0]). These outputs from the last device in a block are connected to the BHI[2:0] inputs of the devices in the downstream blocks (see DEPTH-CASCADING, page 124). 20/159 M7040N Full In (FULI[6:0]). Each signal in this bus is connected to FULO[0] or FULO[1] of an upstream device to generate the FULL signal for the depthcascaded block. For more information, see DEPTH-CASCADING, page 124 to Generate Full for a Block Section. Full Out (FULO[1:0]). FULO[1] and FULO[0] are the same logical signal. One of these two signals must be connected to the FULI of up to four downstream devices in a depth-cascaded table. Bit [0] in the data array indicates if the entry is full (1) or empty (0).This signal is asserted if all of the bits in the data array are '1s.' Refer to Depth-Cascading to Generate a "FULL" Signal, page 124. Full Flag (FULL). When asserted, this signal indicates that the table consisting of many depthcascaded devices is full. Device Identification (ID[4:0]). The binary-encoded device ID for a depth-cascaded system starts at 00000 and goes up to 11110. 11111 is reserved for a special broadcast address that selects all cascaded search engines in the system. On a broadcast read-only, the device with the LDEV bit set to '1' responds. Chip Core Supply (VDD). This is equal to 1.5V. Chip I/O Supply (VDDQ). This is equal to either 2.5 or 3.3V. Test Data In (TDI). This is the Test Access Port's Test Data In. Test Clock (TCK). This is the Test Access Port's Test Clock. Test Data Out (TDO). This is the Test Access Port's Test Data Out. Test Mode Select (TMS). This is the Test Access Port's Test Mode Select. Test Reset (TRST_L). This is the Test Access Port's Test Reset. CLOCKS If the CLK_MODE pin is low, M7040N receives the CLK2X and PHS_L signals. It uses the PHS_L signal to divide CLK2X and generate an internal clock (CLK), as shown in Figure 10. The M7040N uses CLK2X and CLK for internal operations. If the CLK_MODE pin is high, the M7040N receives the CLK1X only. the M7040N uses an internal PLL to double the frequency of CLK1X and then divides Figure 10. Clocks (CLK2X and PHS_L) CLK2X that clock by two to generate a CLK for internal operations, as shown in Figure 11. Note: For the purpose of showing timing diagrams, all such diagrams in this document will be shown in CLK2X mode. For a timing diagram in CLK1X mode, the following substitution can be made (see Figure 12). PHS_L (1) AI04750 CLK Note: Any reference to "CLK Cycles" means 1 cycle of the signal, "CLK." 1. "CLK" is an internal signal. Figure 11. Clocks (CLK1X) CLK1X CLK (1) AI04665 1. "CLK" is an internal signal. 21/159 M7040N Figure 12. Clocks for All Timing Diagrams CLK2X PHS_L (Use for CLK1X MODE) CLK1X (Use for CLK1X MODE) AI04666 PLL USAGE When the device first powers up, it takes 0.5 ms to lock the internal phase-lock loop (PLL). During this locking of the PLL, in addition to 32 extra CLK1X cycles in CLK1X mode and 64 extra cycles in CLK2X mode, the RST_L must be held low for proper initialization of the device. Setup and hold requirements will change in CLK1X mode if the duty cycle of the CLK1X is varied. All signals into the device in CLK1X mode are sampled by a clock that is generated by multiplying CLK1X by two. Since PLL has a locking range, the device will only work between the range of frequencies specified in the timing specification section. REGISTERS All registers in the M7040N are 72 bits wide. The M7040N contains 16 pairs of comparand storage registers, 16 pairs of global mask registers (GMRs), eight search successful index registers and one each of command, information, burst Table 9. Register Overview Address 0-31 32-47, 96-111 48-55 56 57 58 59 60 61-63 Abbreviation COMP0-31 MASKS SSR0-7 COMMAND INFO RBURREG WBURREG NFA - Type R RW R RW R RW RW R - READ, burst WRITE, and next-free address registers. Table 9 provides an overview of all the M7040N registers. The registers are ordered in ascending address order. Each register group is then described in the following subsections. Name 32 Comparand Registers. Stores comparands from the DQ Bus for learning later. 16 Global Mask Registers Pairs. 8 SEARCH Successful Index Registers. Command Register. Information Register. Burst Read Register. Burst Write Register. Next Free Address Register. Reserved 22/159 M7040N Comparand Registers The device contains 32 72-bit comparand registers (16 pairs) dynamically selected in every SEARCH operation to store the comparand presented on the DQ Bus. The LEARN command will later use these registers when executed. The M7040N stores the SEARCH command's Cycle A comparand in the even-numbered register and the Cycle B comparand in the odd-numbered register, as shown in Figure 13. Figure 13. Comparand Register Selection During SEARCH and LEARN Instructions 72 Address Index 0 1 143 0 2 4 6 1 3 5 7 72 0 Mask Registers The device contains 32 72-bit global mask registers (16 pairs) dynamically selected in every SEARCH operation to select the search subfield. The addressing of these registers is explained in Figure 14. The four-bit GMR Index supplied on the command (CMD) bus can apply 16 pairs of global masks during the SEARCH and WRITE operations, as shown below. Note: In 72-bit SEARCH and WRITE operations, the host ASIC must program both the even and odd mask registers with the same values. Each mask bit in the GMRs is used during SEARCH and WRITE operations. In SEARCH operations, setting the mask bit to '1' enables compares; setting the mask bit to '0' disables compares (forced match) at the corresponding bit position. In WRITE operations to the data or mask array, setting the mask bit to '1' enables WRITEs; setting the mask bit to '0' disables WRITEs at the corresponding bit position. Figure 14. Addressing the Global Masks Register Array 72 Address Index 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 143 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 72 0 15 30 31 AI04667 SEARCH and WRITE Command Global Mask Selection AI04668 23/159 M7040N SEARCH-Successful Registers (SSR[0:7]) The device contains eight search successful registers (SSRs) to hold the index of the location where a successful search occurred. The format of each register is described in Table 10. The SEARCH command specifies which SSR stores the index of a specific SEARCH command in Cycle B of the SEARCH Instruction. Subsequently, the host ASIC can use this register to access that data array, mask array, or external SRAM using the index as part of the indirect access address (see Table 20, page 34 and Table 23, page 37). The device with a valid bit set performs a READ or WRITE operation. All other devices suppress the operation. Table 10. SEARCH-Successful Register (SSR) Description Field Range Initial Value Description Index. This is the address of the 72-bit entry where a successful search occurs. The device updates this field only when a search is successful. If a hit occurs in a 144-bit entry-size quadrant, the LSB is '0.' If a hit occurs in a 288-bit entry size quadrant, the two LSBs are '00.' This index updates if the device is either a local or global winner in a SEARCH operation. Reserved. Valid. During SEARCH operation in a depth-cascaded configuration, the device that is a global winner in a match sets this bit to '1.' This bit updates only when the device is a global winner in a SEARCH operation. Reserved. INDEX [15:0] X - [30:16] 0 VALID [31] 0 - [71:32] 0 24/159 M7040N The Command Register Table 11. Command Register Field Descriptions Field Range Initial Value 0 Description Software Reset. If '1,' this bit resets the device, with the same effect as the hardware reset. Internally, it generates a reset pulse lasting for eight CLK cycles. This bit automatically resets to a '0' the reset cycle has completed. Device Enable. If '0,' it keeps the SRAM Bus (SADR, WE_L, CE_L, OE_L, and ALE_L), SSF, and SSV signals in 3-state condition and forces the cascade interface output signals LHO[1:0] and BHO[2:0] to '0.' It also keeps the DQ Bus in input mode. The purpose of this bit is to make sure that there are no bus contentions when the devices power up in the system. Table Size. The host ASIC must program this field to configure the chips into a table of a certain size. This field affects the pipeline latency of the SEARCH and LEARN operations as well as the READ and WRITE accesses to the SRAM (SADR[23:0], CE_L, OE_L, WE_L, ALE_L, SSV, SSF, and ACK). Once programmed, the search latency stays constant. Latency # CLK Cycles with HIGH_SPEED low 00: 1 device 01: 2-8 devices TLSZ [3:2] 01 10: 9-31 devices 11: Reserved Latency # CLK Cycles with HIGH_SPEED high 00: Not supported 01: 1 devices 10: 2-31 devices 11: Reserved Latency of Hit Signals. This field adds latency to the SSF and SSV signals during SEARCH, and ACK signal during SRAM READ access by the following number of CLK cycles. HLAT [6:4] 000 000: 0 001: 1 010: 2 011: 3 100: 4 101: 5 110: 6 111: 7 5 6 4 5 6 SRST [0] DEVE [1] 0 LDEV [7] 0 Last device in the cascade. When set, this is the last device in the depth-cascaded table and is the default driver for the SSF and SSV signals. In the event of a search failure, the device with this bit set drives the hit signals as follows: SSF = 0, SSV = 1 During non-search cycles, the device with this bit set drives the signals as follows: SSF = 0, SSV = 0 25/159 M7040N Field Range Initial Value Description Last device on this SRAM Bus. When set, this device is the last device on this SRAM bus in the depth-cascaded table and is the default driver for the SADR, CE_L, WE_L, and ALE_L signals. In cycles where no M7040N device in a depth-cascaded table drives these signals, this device drives the signals as follows: SADR = FFFFFF, CE_L = 1 WE_L = 1 ALE_L = 1 OE_L is always driven by the device for which this bit is set. Database Configuration. The device is internally divided into eight quadrants of 8K x 72, each of which can be configured as 8K x 72, 4K x 144, or 2K x 288 as follows: 00: 8K x 72 01: 4K x 144 10: 2K x 288 11: low power, partition not used for SEARCH Bits [10:9] apply to configuring the 1st quadrant in the address space. Bits [12:11] apply to configuring the 2nd quadrant in the address space. Bits [14:13] apply to configuring the 3rd quadrant in the address space. Bits [16:15] apply to configuring the 4th quadrant in the address space. Bits [18:17] apply to configuring the 5th quadrant in the address space. Bits [20:19] apply to configuring the 6th quadrant in the address space. Bits [22:21] apply to configuring the 7th quadrant in the address space. Bits [24:23] apply to configuring the 8th quadrant in the address space. Reserved. LRAM [8] 0 CFG [24:9] 0000 0000 0000 0000 [71:25] 0 The Information Register Table 12. Information Register Field Descriptions Field Revision Implementation Reserved Device ID MFID Range [3:0] [6:4] [7] [15:8] [31:16] [71:32] Initial Value 0001 001 0 00000100 0000_0010_0000_1111 Description Revision Number. This is the current device revision number. Numbers start from one and increment by one for each revision of the device. This is the M7040N implementation number. Reserved. This is the Device Identification Number. Manufacturer ID. This field is the same as the manufacturer ID and continuation bits in the TAP controller. Reserved. 26/159 M7040N The Read Burst Address Register (RBURREG) These READ burst address register fields must be programmed before burst read. Table 13. Read Burst Register Description Field Range Initial Value Description Address. This is the starting address of the data array or mask array during a burst READ operation. It automatically increments by 1 for each successive read of the data array or mask array. Once the operation is complete, the contents of this field must be reinitialized for the next operation. Reserved. Length of Burst Access. The device is capable of writing from 4 up to 511 locations in a single burst. The BLEN decrements automatically. Once the operation is complete, the contents of this field must be reinitialized for the next operation. Reserved. ADR [15:0] 0 [18:16] BLEN [27:19] 0 [71:28] The Write Burst Address Register (WBURREG) These WRITE burst address register fields must be programmed before burst write. Table 14. Write Burst Register Description Field Range Initial Value Description Address. This is the starting address of the data array or mask array during a burst WRITE operation. It automatically increments by 1 for each successive write of the data array or mask array. Once the operation is complete, the contents of this field must be reinitialized for the next operation. Reserved. Length of Burst Access. The device is capable of writing from 4 up to 511 locations in a single burst. The BLEN decrements automatically. Once the operation is complete, the contents of this field must be reinitialized for the next operation. Reserved. ADR [15:0] 0 [18:16] BLEN [27:19] 0 [71:28] The NFA Register Bit [0] of each 72-bit data entry is a special bit designated for use in the operation of the LEARN command. In 72-bit quadrants, the bit[0] indicates whether a location is full (bit set to '1') or empty (bit set to '0'). Every WRITE/LEARN command loads the address of first 72-bit location that contains a '0' in the entry's bit[0]. This is stored in the NFA register (see Table 15). If all the bits in a device are set to '1,' the M7040N asserts FULO[1:0] to '1.' In 144-bit-configured quadrants, the LSB of this register is always set to '0.' The host ASIC must set bit '0' and bit 72 in a 144-bit word to either '0' or '1' to indicate full/empty status. Note: Both bits (0 and 72) must be set to '0' or '1' (e.g., '10' or '01' settings are invalid). Table 15. NFA Register Address 60 71 - 16 Reserved 15 - 0 Index 27/159 M7040N SEARCH ENGINE ARCHITECTURE The M7040N consists of 64K x 72-bit storage cells referred to as data bits. There is a mask cell corresponding to each data cell. Figure 15 shows the three organizations of the device based on the value of the CFG bits in the command register. During a SEARCH operation, the search data bit (S), data array bit (D), mask array bit (M) and the global mask bit (G) are used in the following manner to generate a match at that bit position (see Table 16, page 29). The entry with all matched bit positions results in a successful search during a SEARCH operation. In order for a successful search within a device to make the device the local winner in the SEARCH operation, all 72-bit positions must generate a match for a 72-bit entry in 72-bit-configured quadrants, or all 144-bit positions must generate a match for two consecutive even and odd 72-bit entries in quadrants configured as 144 bits, or all Figure 15. M7040N Database Width Configuration 72 144 288 288-bit positions must generate a match for 4 consecutive entries aligned to 4 entry-page boundaries of 72-bit entries in quadrants configured as 288 bits. An arbitration mechanism using a cascade bus determines the global winning device among the local winning devices in a SEARCH cycle. The global winning device drives the SRAM Bus, SSV, and the SSF signals. In case of a SEARCH failure, the devices with the LDEV and LRAM bits set drive(s) the SRAM Bus, SSF, and SSV signals The M7040N device can be configured to contain tables of different widths, even within the same chip. Figure 16, page 29 shows a sample configuration of different widths. Data and Mask Addressing Figure 17, page 29 shows the M7040N data array and mask array addressing procedure. Data Masks 64 K 32 K Masks Data CFG = 0101010101010101 16 K Masks Data CFG = 1010101010101010 CFG = 0000000000000000 AI04669 28/159 M7040N Table 16. Bit Position Match G 0 1 1 1 1 1 M X 0 1 1 1 1 S X X 0 0 1 1 D X X 0 1 0 1 Match 1 1 1 0 0 1 Figure 16. Multi-width Configuration Example 72 8K 72 8K 72 8K 72 8K 4K 4K 2K 2K 144 144 288 288 CFG = 10 10 01 01 11 11 00 00 Inactive (low power) AI04670 Figure 17. M7040N Data and Mask Array Addressing 72 71 0 1 2 3 64 K 0 283 0 4 16K 65532 65533 65534 65535 1 5 2 6 3 7 72 72 72 72 0 143 0 2 4 6 32K 1 3 5 7 72 72 0 CFG = 1010101010101010 (288-bit configuration) 65535 CFG = 0000000000000000 (72-bit Configuration) 65534 65535 CFG = 0101010101010101 (144-bit Configuration) AI04671 29/159 M7040N COMMAND CODES AND PARAMETERS A master device, such as an ASIC controller, issues commands to the M7040N using the Command Valid CMDV signal and the CMD Bus. The following subsections describe the functions of the commands. Command Codes The M7040N implements four basic commands shown in Table 17. The Command Code must be presented to CMD[1:0] while keeping the command valid (CMDV) signal high for two CLK2X cycles. These two CLK2X cycles are designated as "Cycle A" and "Cycle B" when the CLK_MODE pin is low. In CLK2X mode, the controller ASIC must Table 17. Command Codes CMD Code 00 01 10 Command READ WRITE SEARCH Description Reads one of the following: data array, mask array, device registers, or external SRAM. Writes one of the following: data array, mask array, device registers, or external SRAM. Searches the data array for a desired pattern using the specified register from the global mask register array and local mask associated with each data cell. The device has internal storage for up to 16 comparands that it can learn. The device controller can insert these entries at the next free address (as specified by the NFA register) using the LEARN Instruction. align the instructions with the PHS_L signal. The command code must be presented to CMD[1:0] while keeping the CMDV signal high for one CLK1X cycle when the CLK_MODE pin is high. In CLK1X mode the high phase of the CLK1X is designated as Cycle A and the low phase of the CLK1X is designated as Cycle B. The CMD[10:2] field passes the parameters of the command in Cycles A and B. Commands and Command Parameters Table 18, page 31 lists the CMD bus fields that contain the M7040N command parameters as well as their respective cycles. 11 LEARN 30/159 M7040N Table 18. Command Parameters Cmd(1, 2) Cyc A READ B X Global Mask Register Index [3] Global Mask Register Index [3] Global Mask Register Index [3] X X X X 0 Normal WRITE 1 Parallel WRITE 0 Normal WRITE 1 Parallel WRITE 72-bit: 0 144-bit: 1 288-bit:X 0 0 0 0 0 0 0 = Single 1 = Burst 0 = Single 1 = Burst 0 0 10 X 9 X 8 SADR [23] 7 SADR [22] 6 SADR [21] 5 0 4 0 3 0 2 0 = Single 1 = Burst 1 0 0 0 A WRITE B SADR [23] SADR [22] SADR [21] Global Mask Register Index [2:0] Global Mask Register Index [2:0] 0 1 0 0 0 0 = Single 1 = Burst 72-bit or 144-bit: 0 288-bit: 1 in 1st Cycle 0 in 2nd Cycle 0 1 A SEARCH B A LEARN(3) B SADR [23] SADR [22] SADR [21] Global Mask Register Index [2:0] 1 0 Successful SEARCH Register Index[2:0] SADR [23] 0 SADR [22] 0 SADR [21] Mode 0: 72-bit 1: 144-bit Comparand Register Index Comparand Register Index 1 1 0 1 X X Comparand Register Index 1 1 Note: 1. Use only CMD[8:0] and connect the CMD[10:9] to ground with CFG_L low. 2. For a description of CMD[9] and CMD[2] see subsections on search 288-bit configured tables and mixed-size searches with CFG_L high. 3. The 288-bit-configured devices or 288-bit-configured quadrants within devices do not support the LEARN Instruction. 31/159 M7040N READ COMMAND The READ can be a single read of a data array, a mask array, an SRAM, or a register location (CMD[2] = 0). It can be a burst READ (CMD[2] = 1) or mask array locations using an internal auto-incrementing address register (RBURADR). Table 19, page 34 describes each type of READ command. A single-location READ operation lasts six cycles, as shown in Figure 18, page 33. The burst READ adds two cycles for each successive READ. The SADR[23:21] bits supplied in the READ Instruction Cycle A drive SADR[23:21] signals during the READ of an SRAM location. The single READ operation takes six CLK cycles, in the following sequence: - Cycle 1: The host ASIC applies the READ Instruction on the CMD[1:0] (CMD[2] = 0), using CMDV = 1, and the DQ Bus supplies the address, as shown in Table 20, page 34 and Table 21, page 35. The host ASIC selects the M7040N for which ID[4:0] matches the DQ[25:21] lines. If the DQ[25:21] = 11111, the host ASIC selects the M7040N with the LDEV Bit set. The host ASIC also supplies SADR[23:21] on CMD[8:6] in Cycle A of the READ Instruction if the READ is directed to the external SRAM. - Cycle 2: The host ASIC floats DQ[71:0] to 3state condition. - Cycle 3: The host ASIC keeps DQ[71:0] in 3state condition. - Cycle 4: The selected device starts to drive the DQ[71:0] Bus and drives the ACK signal from Z to low. - Cycle 5: The selected device drives the read data from the addressed location on the DQ[71:0] Bus and drives the ACK signal high. - Cycle 6: The selected device floats DQ[71:0] to 3-state condition and drives the ACK signal low. At the termination of Cycle 6, the selected device releases the ACK line to 3-state condition. The READ Instruction is complete, and a new operation can begin. Note: The latency of the SRAM READ will be different than the one described above (see SRAM PIO Access, page 128). Table 20, page 34 lists and describes the format of the READ address for a data array, mask array, or SRAM. In a burst READ operation, the READ lasts 4 + 2n CLK-cycles (where "n" stands for the number of accesses in the burst specified by the BLEN field of the RBURREG). Table 21, page 35 describes the READ address format for the internal registers. Figure 19, page 33 illustrates the timing diagram for the burst READ of the data or mask array. This operation assumes that the host ASIC has programmed the RBURREG with the starting address (ADR) and the length of transfer (BLEN) before initiating the burst READ command. - Cycle 1: The host ASIC applies the READ Instruction on the CMD[1:0] (CMD[2] = 1), using CMDV=1 and the address supplied on the DQ Bus, as shown in Table 22, page 35. The host ASIC selects the M7040N for which ID[4:0] matches the DQ[25:21] lines. If the DQ[25:21] = 11111, the host ASIC selects the M7040N with the LDEV Bit set. - Cycle 2: The host ASIC floats DQ[71:0] to the 3state condition. - Cycle 3: The host ASIC keeps DQ[71:0] in the 3-state condition. - Cycle 4: The selected device starts to drive the DQ[71:0] Bus and drives ACK and EOT from Z to low. - Cycle 5: The selected device drives the READ data from the addressed location on the DQ[71:0] Bus and drives the ACK signal high. Note: Cycles four and five repeat for each additional access until all the accesses specified in the burst length (BLEN) field of RBURREG are complete. On the last transfer, the M7040N drives the EOT signal high. - Cycle (4 + 2n): The selected device drives the DQ[71:0] to 3-state condition and drives the ACK and the EOT signals low. At the termination of Cycle 4 + 2n, the selected device floats the ACK line to 3-state condition. The burst READ Instruction is complete, and a new operation can begin (see Table 22, page 35 for burst READ address formats). 32/159 M7040N Figure 18. Single Location READ Cycle Timing Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 CLK2X PHS_L CMDV CMD[1:0] Read CMD[10:2] A B DQ ACK Address FF Data AI04672 Figure 19. Burst READ of the Data and Mask Arrays (BLEN = 4) Cycle 1 Cycle 2 Cycle 3 Cycle 5 Cycle 7 Cycle 9 Cycle 11 Cycle 4 Cycle 6 Cycle 8 Cycle 10 Cycle 12 CLK2X PHS_L CMDV CMD[1:0] Read CMD[10:2] A B DQ ACK Address FF Data0 FF Data1 FF Data2 FF Data3 EOT AI04673 33/159 M7040N Table 19. READ Command Parameters CMD Parameter CMD[2] 0 Read Command Single Read Description Reads a single location of the data array, mask array, external SRAM, or device registers. All access information is applied on the DQ Bus. Reads a block of locations from the data array or mask array as a burst. The internal register (RBURADR) specifies the starting address and the length of the data transfer from the data array or mask array, and it auto-increments the address for each access. All other access information is applied on the DQ Bus. Note: The device registers and external SRAM can only be read in single-read mode. 1 Burst Read Table 20. Data and Mask Array, SRAM Read Address Format DQ [71:30] DQ [29] DQ [28:26] DQ [25:21] DQ [20:19] DQ [18:16] DQ [15:0] Reserved Successful SEARCH 0: Direct Register Index 1: Indirect (Applicable if DQ[29] is indirect) ID 00: Data Array If DQ[29] is '0,' this field carries address of data array location. If DQ[29] is '1,' the successful search register ID (SSRI) Reserved specified on DQ[28:26] supplies the address of the data array location: {SSR[15:2], SSR[1] | DQ[1], SSR[0] | DQ[0]}(1) If DQ[29] is '0,' this field carries address of mask array location. If DQ[29] is '1,' the successful search register ID (SSRI) Reserved specified on DQ[28:26] supplies the address of the mask array location: {SSR[15:2], SSR[1] | DQ[1], SSR[0] | DQ[0]}(1) If DQ[29] is '0,' this field carries address of SRAM location. If DQ[29] is '1,' the successful search register ID (SSRI) Reserved specified on DQ[28:26] supplies the address of the SRAM location: {SSR[15:2], SSR[1] | DQ[1], SSR[0] | DQ[0]}(1) Reserved Successful SEARCH 0: Direct Register Index 1: Indirect (Applicable if DQ[29] is indirect) ID 01: Mask Array Reserved Successful SEARCH 0: Direct Register Index 1: Indirect (Applicable if DQ[29] is indirect) ID 10: External SRAM Note: 1. "|" stands for Logical OR operation. "{ }" stands for concatenation operator. 34/159 M7040N Table 21. READ Address Format for Internal Registers DQ[71:26] Reserved DQ[25:21] ID DQ[20:19] 11: Register DQ[18:7] Reserved DQ[6:0] Register Address Table 22. READ Address Format for Data and Mask Arrays DQ[71:26] Reserved DQ[25:21] ID DQ[20:19] 00: Data Array DQ[18:16] Reserved DQ[15:0] Do not care. These 16 bits come from the internal register (RBURADR) which increments for each access. Do not care. These 16 bits come from the internal register (RBURADR) which increments for each access. Reserved ID 01: Mask Array Reserved WRITE COMMAND The WRITE can be a single write of a data array, mask array, register, or external SRAM location (CMD[2] = 0). It can be a burst WRITE (CMD[2] = 1) using an internal auto-incrementing address register (WBURADR) of the data array or mask array locations. A single-location WRITE is a three-cycle operation, shown in Figure 20, page 36. The burst WRITE adds one extra cycle for each successive WRITE. The WRITE operation sequence is as follows: - Cycle 1A: The host ASIC applies the WRITE Instruction on the CMD[1:0] (CMD[2] = 0), using CMDV=1 and the address supplied on the DQ Bus, as shown in Table 23, page 37. The host ASIC also supplies the index to the global mask register to mask the write to the data array or mask array location in {CMD[10], CMD[5:3]}. For SRAM WRITEs, the host ASIC must supply the SADR[23:21] on CMD[8:6]. The host ASIC sets CMD[9] to '0' for the normal WRITE. - Cycle 1B: The host ASIC continues to apply the WRITE Instruction to the CMD[1:0] (CMD[2] = 0), using CMDV = 1 and the address supplied on the DQ Bus. The host ASIC continues to supply the global mask register index to mask the WRITE to the data or mask array locations in {CMD[10], CMD[5:3]}. The host ASIC selects the device where ID[4:0] matches the DQ[25:21] lines, or it selects all the devices when DQ[25:21] = 11111. - Cycle 2: The host ASIC drives the DQ[71:0] with the data to be written to the data array, mask array, external SRAM, or register location of the selected device. - Cycle 3: Idle cycle. At the termination of this cycle, another operation can begin. Note: The latency of the SRAM WRITE will be different than the one described above (see SRAM PIO Access, page 128). The burst WRITE operation lasts for n + 2 CLK cycles (where n signifies the number of accesses in the burst as specified in the BLEN field of the WBURREG register, please see Figure 21, page 37). This operation assumes that the host ASIC has programmed the WBURREG with the starting address (ADR) and the length of transfer (BLEN) before initiating the burst write command (see Table 25, page 38 for format). The sequence is as follows: - Cycle 1A: The host ASIC applies the WRITE Instruction on the CMD[1:0] (CMD[2] = 1), using CMDV = 1 and the address supplied on the DQ Bus, as shown in Table 25, page 38. The host ASIC also supplies the index to the global mask register to mask the write to the data or mask array locations in {CMD[10], CMD[5:3]}. The host ASIC sets ASIC sets CMD[9] to '0' for the normal WRITE. - Cycle 1B: The host ASIC continues to apply the WRITE Instruction on the CMD[1:0] (CMD[2] = 0), using CMDV = 1 and the address supplied on the DQ Bus. The host ASIC continues to supply the global mask register index to mask the WRITE to the data or mask array locations in {CMD[10], CMD[5:3]}. The host ASIC selects the device where ID[4:0] matches the DQ[25:21] lines, or it selects all the devices when DQ[25:21] = 11111. 35/159 M7040N - Cycle 2: The host ASIC drives the DQ[71:0] with the data to be written to the data array or mask array location of the selected device. The M7040N writes the data from the DQ[71:0] Bus only to the subfield that has the corresponding mask bit set to '1' in the global mask register specified by the index {CMD[10], CMD[5:3]} and supplied in Cycle 1. - Cycles 3 to n + 1: The host ASIC drives the DQ[71:0] with the data to be written to the next data array or mask array location (addressed by the auto-increment ADR field of the WBURREG register) of the selected device. Figure 20. Single Location WRITE Cycle Timing The M7040N writes the data on the DQ[71:0] Bus only to the subfield that has the corresponding mask bit set to '1' in the global mask register specified by the index {CMD[10], CMD[5:3]} and supplied in Cycle 1. The M7040N drives the EOT signal low from Cycle 3 to Cycle n; the M7040N drives the EOT signal high in Cycle n + 1 (n is specified in the BLEN field of the WBURREG). - Cycle n + 2: The M7040N drives the EOT signal low. At the termination of the Cycle n + 2, the M7040N floats the EOT signal to a 3-state, and a new instruction can begin. Cycle 0 CLK2X PHS_L CMDV CMD[1:0] CMD[10:2] DQ Cycle 1 Cycle 2 Cycle 3 Cycle 4 Write A B Address Data X AI04674 36/159 M7040N Figure 21. Burst WRITE of the Data and Mask Arrays (BLEN = 4) Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 CLK2X PHS_L CMDV CMD[1:0] Write CMD[10:2] A B DQ EOT Address Data0 Data1 Data2 Data3 X AI04675 Table 23. (Single) WRITE Address Format for Data and Mask Arrays or SRAM DQ [71:30] DQ [29] DQ [28:26] Successful SEARCH Register Index (Applicable if DQ[29] is indirect) Successful SEARCH Register Index (Applicable if DQ[29] is indirect) Successful SEARCH Register Index (Applicable if DQ[29] is indirect) DQ [25:21] DQ [20:19] DQ [18:16] DQ [15:0] If DQ[29] is '0,' this field carries the address of the data array location. If DQ[29] is '1,' the successful search register specified by DQ[28:26] supplies the address of the data array location: {SSR[15:2], SSR[1] | DQ[1], SSR[0] | DQ[0]}(1) If DQ[29] is '0,' this field carries address of the mask array location. If DQ[29] is '1,' the successful search register specified by DQ[28:26] supplies the address of the mask array location: {SSR[15:2], SSR[1] | DQ[1], SSR[0] | DQ[0]}(1) If DQ[29] is '0,' this field carries address of the data SRAM location. If DQ[29] is '1,' the successful search register specified by DQ[28:26] supplies the address of the SRAM location: {SSR[15:2], SSR[1] | DQ[1], SSR[0] | DQ[0]}(1) Reserved 0: Direct 1: Indirect ID 00: Data Array Reserved Reserved 0: Direct 1: Indirect ID 01: Mask Array Reserved Reserved 0: Direct 1: Indirect ID 10: External SRAM Reserved Note: 1. "|" stands for Logical OR operation. "{ }" stands for concatenation operator. 37/159 M7040N Table 24. WRITE Address Format for Internal Registers DQ[71:26] Reserved DQ[25:21] ID DQ[20:19] 11: Register DQ[18:7] Reserved DQ[6:0] Register address Table 25. WRITE Address Format for Data and Mask Array (Burst Write) DQ [71:26] Reserved DQ [25:21] ID DQ [20:19] 00: Data array DQ [18:16] Reserved DQ [15:0] Don't care. These 16 bits come from the internal register (WBURADR), which increments with each access. Don't care. These 16 bits come from the internal register (WBURADR), which increments with each access. Reserved ID 01: Mask array Reserved Parallel WRITE In order to write the data and mask arrays faster for initialization, testing, or diagnostics, many locations can be written simultaneously in the M7040N device. When CMD[9] is set in Cycles A and B of the WRITE command during a WRITE to the data or mask arrays, the address present on DQ[10:1] that specifies 64 locations in a device is used and 64 72-bit locations are simultaneously written in either the data or mask array. SEARCH COMMAND The M7040N (Silicon) Search Engine can be configured in four ways: 1. 72-bit 2. 144-bit (page ) 3. 288-bit (page ) 4. Mixed-sizes on tables configured with different widths using an M7040N with CFG_L low or CFG_L high (page ) 72-bit Configuration with Single Device The hardware diagram of the search subsystem of a single device is shown in Figure 22. Figure 23, page 40 shows the timing diagram for a SEARCH operation in the 72-bit configuration (CFG = 0000000000000000) for one set of parameters. This illustration assumes that the host ASIC has programmed TLSZ to '00,' HLAT to '000,' LRAM to '1,' and LDEV to '1' in the command register. The following is the sequence of operations for a single 72-bit SEARCH command. - Cycle A: The host ASIC drives CMDV high and applies the SEARCH command code ('10') on CMD[1:0] signals. {CMD[10], CMD[5:3] must be driven with the index to the global mask register pair for use in the SEARCH operation. CMD[8:6] signals must be driven with the same bits that will be driven on SADR[23:21] by this device if it has a hit. DQ[71:0] must be driven with the 72bit data to be compared. The CMD[2] signal must be driven to Logic '0.' - Cycle B: The host ASIC continues to drive CMDV high and applies the SEARCH command ('10') on CMD[1:0]. CMD[5:2] must be driven by the index of the comparand register pair for storing the 144-bit word presented on the DQ Bus during Cycles A and B. CMD[8:6] signals must be driven with the index of the SSR that will be used for storing the address of the matching entry and the Hit Flag (see SEARCH-Successful Registers (SSR[0:7]), page 24). The DQ[71:0] continues to carry the 72-bit data to be compared. Note: In the 72-bit configuration, the host ASIC must supply the same data on DQ[71:0] during both Cycles A and B. The even and odd pair of GMRs selected for the comparison must be programmed with the same value. 38/159 M7040N The logical 72-bit SEARCH operation is shown in Figure 24, page 41. The entire table consisting of 72-bit entries is compared to a 72-bit word K (presented on the DQ Bus in both Cycles A and B of the command) using the GMR and the local mask bits. The effective GMR is the 72-bit word specified by the identical value in both even and odd GMR pairs selected by the GMR Index in the command's Cycle A. The 72-bit word K (presented on the DQ Bus in both Cycles A and B of the command) is also stored in both even and odd comparand register pairs selected by the Comparand Register Index in the command's Cycle B. In a x72 configuration, only the even comparand register can be subsequently used by the LEARN command. The word K (presented on the DQ Bus in both Cycles A and B of the command) is compared with each entry in the table starting at location "0." The first matching entry's location address, "L," is the winning address that is driven as part of the SRAM address on the SADR[23:0] lines (see SRAM ADDRESSING, page 128). The SEARCH command is a pipelined operation and executes a SEARCH at half the rate of the frequency of CLK2X for 72-bit searches in x72-configured tables. The latency of SADR, CE_L, ALE_L, WE_L, SSV, and SSF from the 72-bit SEARCH command cycle (two CLK2X cycles) is shown in Table 26, page 41. The latency of a SEARCH from command to SRAM access cycle is 4 for a single device in the table and TLSZ = 00. In addition, SSV and SSF shift further to the right for different values of HLAT, as specified in Table 27, page 41. Figure 22. Hardware Diagram for a Table with One Device BHI[2:0] 6 5 4 3 LHI 2 1 0 DQ[71:0] CMDV, CMD[10:0] SSF, SSV BHI[2:0] LHO[1] LHO[0] M7040 SRAM AI04677 39/159 M7040N Figure 23. 72-Bit Configuration SEARCH Timing Diagram for One Device Cycle 2 Cycle 4 Cycle 6 Cycle 8 Cycle 10 Cycle 1 Cycle 3 Cycle 5 Cycle 7 Cycle 9 CLK2X PHS_L CMDV Search1 Search3 01 Search2 01 01 Search4 CMD[1:0] 01 CMD[10:2] A B A B A B A B DQ D1 D2 D3 D4 SADR[23:0] CE_L A1 A3 1 0 1 0 1 ALE_L WE_L 1 0 1 0 1 1 0 1 0 1 0 1 0 1 0 OE_L SSV SSF 0 1 0 0 1 0 1 0 Search1 Search3 Hit Hit Search4 Search2 Miss Miss CFG = 0000000000000000, HLAT = 000, TLSZ = 00, LRAM = 1, LDEV = 1 AI04676 40/159 M7040N Figure 24. x72 Table with One Device 71 0 Comparand Register (even) GMR K Location 71 address 0 1 2 3 0 71 0 Comparand Register (even) K Comparand Register (odd) K L (First matching entry) 65535 CFG = 0000000000000000 (288-bit Configuration) AI04678 Table 26. Latency of SEARCH from Instruction to SRAM Access Cycle, 72-bit # of devices 1 (TLSZ = 00) 2-8 (TLSZ = 01) 2-31 (TLSZ = 10) Max Table Size 64K x 72-bit 512K x 72-bit 1984K x 72-bit Latency in CLK Cycles 4 5 6 Table 27. Shift of SSF and SSV from SADR HLAT 000 001 010 011 100 101 110 111 Number of CLK Cycles 0 1 2 3 4 5 6 7 41/159 M7040N 72-bit SEARCH on Tables Configured as x72 Using up to Eight M7040N Devices Registers (SSR[0:7]), page 24). The DQ[71:0] The hardware diagram of the search subsystem of eight devices is shown in Figure 25, page 43. The continues to carry the 72-bit data to be comfollowing are the parameters programmed into the pared. eight devices: Note: For 72-bit searches, the host ASIC must - First seven devices (device 0-6): supply the same data on DQ[71:0] during both Cycles A and B. The even and odd pair of CFG = 0000000000000000, TLSZ = 01, GMRs selected for the comparison must be proHLAT = 010, LRAM = 0, and LDEV = 0. grammed with the same value. - Eighth device (device 7): The logical 72-bit SEARCH operation is shown in CFG = 0000000000000000, TLSZ = 01, Figure 26, page 44. The entire table with eight deHLAT = 010, LRAM = 1, and LDEV = 1. vices of 72-bit entries is compared to a 72-bit word K (presented on the DQ Bus in both Cycles A and Note: All eight devices must be programmed with B of the command) using the GMR and the local the same values for TLSZ and HLAT. Only the last mask bits. The effective GMR is the 72-bit word device in the table (Device 7 in this case) must be specified by the identical value in both even and programmed with LRAM = 1 and LDEV = 1. All odd GMR pairs in each of the eight devices and other upstream devices (Devices 0 through 6 in selected by the GMR Index in the command's Cythis case) must be programmed with LRAM = 0 cle A. The 72-bit word K (presented on the DQ Bus and LDEV = 0. in both Cycles A and B of the command) is also Figure 27, page 45 shows the timing diagram for a stored in both even and odd comparand register SEARCH command in the 72-bit-configured table pairs (selected by the Comparand Register Index of eight devices for Device 0. Figure 28, page 46 in command Cycle B) in each of the eight devices. shows the timing diagram for a SEARCH comIn the x72 configuration, only the even comparand mand in the 72-bit-configured table of eight devicregister can subsequently be used by the LEARN es for Device 1. Figure 29, page 47 shows the command in one of the devices (only the first nontiming diagram for a SEARCH command in the full device). The word K (presented on the DQ Bus 72-bit-configured table of eight devices for Device in both Cycles A and B of the command) is com7 (the last device in this specific table). For these pared with each entry in the table starting at locatiming diagrams four 72-bit searches are pertion "0." The first matching entry's location formed sequentially. HIT/MISS assumptions were address, "L," is the winning address that is driven made as shown below in Table 28. as part of the SRAM address on the SADR[23:0] The sequence of operation for a 72-bit SEARCH lines (see SRAM ADDRESSING, page 128). The command is as follows:] global winning device will drive the bus in a specific cycle. On a global miss cycle the device with - Cycle A: The host ASIC drives CMDV high and LRAM = 1 (default driving device for the SRAM applies the SEARCH command code ('10') on Bus) and LDEV = 1 (default driving device for SSF CMD[1:0] signals. {CMD[10], CMD[5:3] must be and SSV signals) will be the default driver for such driven with the index to the global mask register missed cycles. pair for use in the SEARCH operation. CMD[8:6] signals must be driven with the same bits that The SEARCH command is a pipelined operation will be driven on SADR[23:21] by this device if it and executes a search at half the rate of the frehas a hit. DQ[71:0] must be driven with the 72quency of CLK2X for 72-bit searches in x72-conbit data to be compared. The CMD[2] signal figured tables. The latency of SADR, CE_L, must be driven to Logic '0.' ALE_L, WE_L, SSV, and SSF from the 72-bit SEARCH command cycle (two CLK2X cycles) is - Cycle B: The host ASIC continues to drive shown in Table 29, page 48 CMDV high and applies the SEARCH command ('10') on CMD[1:0]. CMD[5:2] must be driven by The latency of the search from command to SRAM the index of the comparand register pair for storaccess cycle is 5 for up to eight devices in the table ing the 144-bit word presented on the DQ Bus (TLSZ = 01). SSV and SSF also shift further to the during Cycles A and B. CMD[8:6] signals must right for different values of HLAT, as specified in be driven with the index of the SSR that will be Table 30, page 48. used for storing the address of the matching entry and the Hit Flag (see SEARCH-Successful 42/159 M7040N Table 28. Hit/Miss Assumption Search Number Device 0 Device 1 Device 2-6 Device 7 1 Hit Miss Miss Miss 2 Miss Hit Miss Miss 3 Hit Hit Miss Hit 4 Hit Miss Miss Hit Figure 25. Hardware Diagram for a Table with Eight Devices SRAM BHI[2:0] LHO[1] 6 5 4 M7040 #0 3 LHI 2 1 0 LHO[0] SSF, SSV BHI[2:0] LHO[1] M7040 #1 6 5 4 3 LHI 2 1 LHO[0] 0 DQ[71:0] CMDV CMD[10:0] BHI[2:0] LHO[1] 6 5 4 3 2 LHI LHO[0] 1 0 M7040 #2 BHI[2:0] LHO[1] 6 5 4 M7040 #3 3 LHI LHO[0] 2 1 0 BHI[2:0] 6 5 4 M7040 #4 32 LHI 1 0 LHO[0] BHI[2:0] 3 2 1 LHI 0 6 M7040 #5 5 4 LHI LHO[0] BHI[2:0] 3 2 1 LHI 0 6 M7040 #6 5 4 LHI LHO[0] BHI[2:0] 3 2 1 LHI 0 6 M7040 #7 5 LHI 4 BHO[0] BHO[1] BHO[0] BHO[1] BHO[2] BHO[2] LHO[1] LHO[0] AI04679 43/159 M7040N Figure 26. x72 Table with Eight Devices 71 Must be the same in each of the eight devices GMR K Location 71 address 0 1 2 3 0 0 71 0 Comparand Register (even) K Comparand Register (odd) K L (First matching entry) 524287 Will be the same in each of the eight devices CFG = 0000000000000000 (72-bit Configuration) AI04683 44/159 M7040N Timing Diagrams for x72 Using up to Eight M7040N Devices Figure 27. Timing Diagram for 72-bit SEARCH For Device 0 Cycle 2 Cycle 4 Cycle 6 Cycle 8 Cycle 10 Cycle 1 Cycle 3 Cycle 5 Cycle 7 Cycle 9 CLK2X PHS_L CMDV Search1 Search3 01 Search2 01 01 Search4 CMD[1:0] 01 CMD[10:2] A B A B A B A B DQ (LHI[6:0])(1) LHO[1:0](2) SADR[23:0] CE_L z z z 0 D1 D2 D3 D4 A1 z z A3 z z 0 z 0 z z z z Search1 (This device is the global winner.) z 0 z 0 z ALE_L WE_L OE_L SSV SSF 1 1 1 1 z z 1 1 z z CFG = 0000000000000000, HLAT = 010, TLSZ = 01, LRAM = 0, LDEV = 0 Search2 (Miss on this device.) Search3 (This device is the global winner.) Search4 (Miss on this device.) AI04680 Note: 1. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0]. 2. Each bit in LHO[1:0] is the same logical signal. 45/159 M7040N Figure 28. Timing Diagram for 72-bit SEARCH For Device 1 Cycle 2 Cycle 4 Cycle 6 Cycle 8 Cycle 10 Cycle 1 Cycle 3 Cycle 5 Cycle 7 Cycle 9 CLK2X PHS_L CMDV Search1 Search3 01 Search2 01 01 Search4 CMD[1:0] 01 CMD[10:2] A B A B A B A B DQ (LHI[6:0])(1) LHO[1:0](2) SADR[23:0] CE_L ALE_L z z D1 D2 D3 D4 A2 z 0 z 0 z WE_L OE_L SSV SSF z z z z Search1 (Miss on this device.) 1 z 1 1 z z CFG = 0000000000000000, HLAT = 010, TLSZ = 01, LRAM = 0, LDEV = 0 Search2 (This device is global winner.) Search3 (Local winner but not global winner.) Search4 (Miss on this device.) AI04681 Note: 1. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0]. 2. Each bit in LHO[1:0] is the same logical signal. 46/159 M7040N Figure 29. Timing Diagram for 72-bit SEARCH For Device 7 (Last Device) Cycle 2 Cycle 4 Cycle 6 Cycle 8 Cycle 10 Cycle 1 Cycle 3 Cycle 5 Cycle 7 Cycle 9 CLK2X PHS_L CMDV Search1 Search3 01 Search2 01 01 Search4 CMD[1:0] 01 CMD[10:2] A B A B A B A B DQ |(LHI[6:0])(1) LHO[1:0](2) SADR[23:0] CE_L ALE_L WE_L OE_L SSV SSF 0 0 D1 D2 D3 D4 z A2 z z z 0 0 1 0 0 0 Search1 (Miss on this device.) 1 1 z 1 z 0 0 CFG = 0000000000000000, HLAT = 010, TLSZ = 01, LRAM = 1, LDEV = 1 Search2 (Miss on this device.) Search3 (Local winner but not global winner.) Search4 (Global winner.) AI04682 Note: 1. |(LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0]. 2. Each bit in LHO[1:0] is the same logical signal. 47/159 M7040N Table 29. Latency of SEARCH from Instruction to SRAM Access Cycle # of devices 1 (TLSZ = 00) 1-8 (TLSZ = 01) 1-31 (TLSZ = 10) Max Table Size 64K x 72-bit 512K x 72-bit 1984K x 72-bit Latency in CLK Cycles 4 5 6 Table 30. Shift of SSF and SSV from SADR HLAT 000 001 010 011 100 101 110 111 Number of CLK Cycles 0 1 2 3 4 5 6 7 72-bit Search on Tables Configured as x72 Using Up To 31 M7040N Devices one device with a matching entry in each of the The hardware diagram of the search subsystem of 31 devices is shown in Figure 30, page 50. Each blocks. Figure 33, page 53 shows the timing diagram for a SEARCH command in the 72-bit-conof the four blocks in the diagram represents eight M7040N devices (except the last, which has seven figured table of 31 devices for each of the eight devices). The diagram for a block of eight devices devices in Block Number 0. Figure 34, page 54 is shown in Figure 31, page 51. The following are shows a timing diagram for a SEARCH command the parameters programmed into the 31 devices: in the 72-bit-configured table of 31 devices for the all the devices in Block Number 1 (above the win- First thirty devices (devices 0-29): ning device in that block). Figure 35, page 55 CFG = 0000000000000000, TLSZ = 10, shows the timing diagram for the globally winning HLAT = 001, LRAM = 0, and LDEV = 0. device (defined as the final winner within its own and all blocks) in Block Number 1. Figure 36, page - Thirty-first device (device 30): 56 shows the timing diagram for all the devices beCFG = 0000000000000000, TLSZ = 10, low the globally winning device in Block Number 1. HLAT = 001, LRAM = 1, and LDEV = 1. Figure 37, page 57, Figure 38, page 58, and FigNote: All 31 devices must be programmed with the ure 39, page 59 show the timing diagrams of the same values for TLSZ and HLAT. Only the last dedevices above the globally winning device, the glovice in the table must be programmed with bally winning device, and the devices below the LRAM = 1 and LDEV = 1 (Device 30 in this case). globally winning device, respectively, for Block All other upstream devices must be programmed Number 2. Figure 40, page 60, Figure 41, page 61, with LRAM = 0 and LDEV = 0 (Devices 0 through Figure 42, page 62, and Figure 43, page 63 show 29 in this case). the timing diagrams of the devices above globally winning device, the globally winning device, and The timing diagrams referred to in this paragraph the devices below the globally winning device exreference the HIT/MISS assumptions defined in cept the last device (Device 30), respectively, for Table 31, page 49. For the purpose of illustrating Block Number 3. the timings, it is further assumed that there is only 48/159 M7040N The following is the sequence of operation for a single 72-bit SEARCH command (also refer to Command Codes, page 30). - Cycle A: The host ASIC drives the CMDV high and applies SEARCH command code ('10') on CMD[1:0] signals. {CMD[10],CMD[5:3]} signals must be driven with the index to the GMR pair for use in this SEARCH operation. CMD[8:6] signals must be driven with the same bits that will be driven on SADR[23:21] by this device if it has a hit. DQ[71:0] must be driven with the 72bit data to be compared. The CMD[2] signal must be driven to a logic '0.' - Cycle B: The host ASIC continues to drive the CMDV high and applies SEARCH command ('10') on CMD[1:0]. CMD[5:2] must be driven by the index of the comparand register pair for storing the 144-bit word presented on the DQ Bus during Cycles A and B. CMD[8:6] signals must be driven with the index of the SSR that will be used for storing the address of the matching entry and the Hit Flag (see SEARCH-Successful Registers (SSR[0:7]), page 24). The DQ[71:0] continues to carry the 72-bit data to be compared. Note: For 72-bit searches, the host ASIC must supply the same 72-bit data on DQ[71:0] during both Cycles A and B. The even and odd pair of GMRs selected for the comparison must be programmed with the same value. The logical 72-bit SEARCH operation is shown in Figure 32, page 52. The entire table (31 devices of 72-bit entries) is compared to a 72-bit word K (presented on the DQ Bus in both Cycles A and B of the command) using the GMR and the local mask bits. The effective GMR is the 72-bit word specified by the identical value in both even and odd GMR pairs in each of the eight devices and selected by the GMR Index in the command's Cycle A. The 72-bit word K (presented on the DQ Bus in both Cycles A and B of the command) is also stored in both even and odd comparand register pairs in each of the eight devices and selected by the Comparand Register Index in command's CyTable 31. Hit/Miss Assumption Search Number Block 0 Block 1 Block 2 Block 3 1 Miss Miss Miss Hit 2 Miss Miss Hit Hit 3 Miss Hit Hit Miss 4 Miss Miss Miss Miss cle B. In the x72 configuration, the even comparand register can be subsequently used by the LEARN command only in the first non-full device. The word K (presented on the DQ Bus in both Cycles A and B of the command) is compared with each entry in the table starting at location "0." The first matching entry's location address, "L," is the winning address that is driven as part of the SRAM address on the SADR[23:0] lines (see SRAM ADDRESSING, page 128). The global winning device will drive the bus in a specific cycle. On global miss cycles the device with LRAM = 1 and LDEV = 1 will be the default driver for such missed cycles. The SEARCH command is a pipelined operation and executes a search at half the rate of the frequency of CLK2X for 72-bit searches in x72-configured tables. The latency of SADR, CE_L, ALE_L, WE_L, SSV, and SSF from the 72-bit SEARCH command cycle (two CLK2X cycles) is shown in Table 32, page 64. For up to 31 devices in the table (TLSZ = 10), search latency from command to SRAM access cycle is 6. In addition, SSV and SSF shift further to the right for different values of HLAT, as specified in Table 33, page 64. The 72-bit SEARCH operation is pipelined and executes as follows: - Four cycles from the SEARCH command, each of the devices knows the outcome internal to it for that operation; - In the fifth cycle after the SEARCH command, the devices in a block arbitrate for a winner amongst them (a "block" being defined as less than or equal to eight devices resolving the winner within them using the LHI[6:0] and LHO[1:0] signalling mechanism); - In the sixth cycle after the SEARCH command, the blocks (of devices) resolve the winning block through the BHI[2:0] and BHO[2:0] signalling mechanism. The winning device within the winning block is the global winning device for a SEARCH operation. 49/159 M7040N Figure 30. Hardware Diagram for a Table with 31 Devices BHI[2] BHI[1] BHI[0] GND SSF, SSV BHO[2] Block of 8 M7040s, Block 0 (Devices 0-7) BHO[1] BHO[0] SRAM BHI[2] BHI[1] BHI[0] GND Block of 8 M7040s, Block 1 (Devices 8-15) BHO[2] BHO[1] BHO[0] BHI[2] BHI[1] BHI[0] GND Block of 8 M7040s, Block 2 (Devices 16-23) BHO[2] BHO[1] BHO[0] BHI[2] BHI[1] BHI[0] DQ[71:0] CMD[10:0], CMDV Block of 7 M7040s, Block 3 (Devices 24-30) BHO[2] BHO[1] BHO[0] AI04684 50/159 M7040N Figure 31. Hardware Diagram for a Block of Up To Eight Devices SRAM BHI[2:0] LHO[1] 6 5 4 BHI[2:0] M7040 #0 3 LHI 2 1 0 LHO[0] BHI[2:0] DQ[71:0] CMDV CMD[10:0] BHI[2:0] LHO[1] M7040 #1 6 5 4 3 LHI 2 1 0 LHO[0] 6 LHO[1] 5 4 SSV, SSF M7040 #2 3 2 1 LHI LHO[0] 0 BHI[2:0] LHO[1] 6 5 4 M7040 #3 3 2 LHI LHO[0] 1 0 BHI[2:0] 6 5 4 M7040 #4 32 LHI 1 0 LHO[0] BHI[2:0] 3 2 1 LHI 0 6 M7040 #5 5 4 LHI LHO[0] BHI[2:0] 3 2 1 LHI 0 6 M7040 #6 5 4 LHI LHO[0] BHI[2:0] 3 2 1 LHI 0 6 M7040 #7 5 LHI 4 BHO[0] BHO[1] BHO[0] BHO[1] BHO[2] BHO[2] LHO[1] LHO[0] AI04685 51/159 M7040N Figure 32. x72 Table with 31 Devices 71 Must be the same for each of the 31 devices GMR K Location 71 address 0 1 2 3 0 0 71 0 Comparand Register (even) K Comparand Register (odd) K L (First matching entry) 2031615 Will be the same in each of the 31 devices CFG = 0000000000000000 (72-bit Configuration) AI04696 52/159 M7040N Timing Diagrams for x72 Using Up To 31 M7040N Devices Figure 33. Timing Diagram for Each Device in Block Number 0 (Miss on Each Device) Cycle 2 Cycle 4 Cycle 6 Cycle 8 Cycle 10 Cycle 1 Cycle 3 Cycle 5 Cycle 7 Cycle 9 CLK2X PHS_L CMDV Search1 Search3 01 Search2 01 01 Search4 CMD[1:0] 01 CMD[10:2] A B A B A B A B DQ (LHI[6:0])(1) LHO[1:0](2) (BHI[2:0]) BHO[2:0] (3) (4) 0 0 0 0 z z z z z z z D1 D2 D3 D4 SADR[23:0] CE_L ALE_L WE_L OE_L SSV SSF CFG = 0000000000000000, HLAT = 001, TLSZ = 10, LRAM = 0, LDEV = 0 Search1 (Miss on this device.) Search2 (Miss on this device.) Search3 (Miss on this device.) Search4 (Miss on this device.) AI04686 Note: 1. 2. 3. 4. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0]. Each bit in LHO[1:0] is the same logical signal. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0]. Each bit in BHO[2:0] is the same logical signal. 53/159 M7040N Figure 34. Timing Diagram for Each Device Above the Winning Device in Block Number 1 Cycle 2 Cycle 4 Cycle 6 Cycle 8 Cycle 10 Cycle 1 Cycle 3 Cycle 5 Cycle 7 Cycle 9 CLK2X PHS_L CMDV Search1 Search3 01 Search2 01 01 Search4 CMD[1:0] 01 CMD[10:2] A B A B A B A B DQ (LHI[6:0]) (1) 0 0 0 0 z z z z z z z D1 D2 D3 D4 LHO[1:0](2) (BHI[2:0]) (3) BHO[2:0](4) SADR[23:0] CE_L ALE_L WE_L OE_L SSV SSF CFG = 0000000000000000, HLAT = 001, TLSZ = 10, LRAM = 0, LDEV = 0 Search1 (Miss on this device.) Search2 (Miss on this device.) Search3 (Miss on this device.) Search4 (Miss on this device.) AI04686 Note: 1. 2. 3. 4. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0]. Each bit in LHO[1:0] is the same logical signal. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0]. Each bit in BHO[2:0] is the same logical signal. 54/159 M7040N Figure 35. Timing Diagram for the Globally Winning Device in Block Number 1 Cycle 2 Cycle 4 Cycle 6 Cycle 8 Cycle 10 Cycle 1 Cycle 3 Cycle 5 Cycle 7 Cycle 9 CLK2X PHS_L CMDV Search1 Search3 01 Search2 01 01 Search4 CMD[1:0] 01 CMD[10:2] A BABABAB DQ D1 0 D2 D3 D4 (LHI[6:0])(1) LHO[1:0](2) (BHI[2:0])(3) BHO[2:0](4) SADR[23:0] CE_L ALE_L WE_L OE_L SSV SSF 0 0 0 z z z z z z A3 0 0 1 z z z z Search1 (Miss on this device.) Search2 (Miss on this device.) Search3 (This device global winner.) Search4 (Miss on this device.) z z z CFG = 0000000000000000, HLAT = 001, TLSZ = 10, LRAM = 0, LDEV = 0 AI04687 Note: 1. 2. 3. 4. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0]. Each bit in LHO[1:0] is the same logical signal. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0]. Each bit in BHO[2:0] is the same logical signal. 55/159 M7040N Figure 36. Timing Diagram for Devices Below the Winning Device in Block Number 1 Cycle 2 Cycle 4 Cycle 6 Cycle 8 Cycle 10 Cycle 1 Cycle 3 Cycle 5 Cycle 7 Cycle 9 CLK2X PHS_L CMDV Search1 Search3 01 Search2 01 01 Search4 CMD[1:0] 01 CMD[10:2] A BABABAB DQ D1 D2 D3 D4 (LHI[6:0])(1) LHO[1:0](2) (BHI[2:0])(3) BHO[2:0](4) SADR[23:0] CE_L ALE_L WE_L OE_L SSV SSF 0 0 0 0 z z z z z z z Search1 (Miss on this device.) Search2 (Miss on this device.) CFG = 0000000000000000, HLAT = 001, TLSZ = 10, LRAM = 0, LDEV = 0 Search3 (Miss on this device.) Search4 (Miss on this device.) AI04688 Note: 1. 2. 3. 4. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0]. Each bit in LHO[1:0] is the same logical signal. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0]. Each bit in BHO[2:0] is the same logical signal. 56/159 M7040N Figure 37. Timing Diagram for Devices Above the Winning Device in Block Number 2 Cycle 2 Cycle 4 Cycle 6 Cycle 8 Cycle 10 Cycle 1 Cycle 3 Cycle 5 Cycle 7 Cycle 9 CLK2X PHS_L CMDV Search1 Search3 01 Search2 01 01 Search4 CMD[1:0] 01 CMD[10:2] A BABABAB DQ D1 0 0 D2 D3 D4 (LHI[6:0])(1) LHO[1:0](2) (BHI[2:0])(3) BHO[2:0](4) SADR[23:0] CE_L ALE_L WE_L OE_L SSV SSF 0 0 z z z z z z z Search1 (Miss on this device.) Search2 (Miss on this device.) CFG = 0000000000000000, HLAT = 001, TLSZ = 10, LRAM = 0, LDEV = 0 Search3 (Miss on this device.) Search4 (Miss on this device.) AI04689 Note: 1. 2. 3. 4. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0]. Each bit in LHO[1:0] is the same logical signal. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0]. Each bit in BHO[2:0] is the same logical signal. 57/159 M7040N Figure 38. Timing Diagram for the Globally Winning Device in Block Number 2 Cycle 2 Cycle 4 Cycle 6 Cycle 8 Cycle 10 Cycle 1 Cycle 3 Cycle 5 Cycle 7 Cycle 9 CLK2X PHS_L CMDV Search1 Search3 01 Search2 01 01 Search4 CMD[1:0] 01 CMD[10:2] A BABABAB DQ D1 0 D2 D3 D4 (LHI[6:0])(1) LHO[1:0](2) (BHI[2:0])(3) BHO[2:0](4) 0 0 0 z z 0 z 0 z z z SADR[23:0] CE_L ALE_L WE_L OE_L SSV SSF A2 z z z z Search1 (Miss on this device.) 1 z 1 1 z z CFG = 0000000000000000, HLAT = 001, TLSZ = 10, LRAM = 0, LDEV = 0 Search2 (Global winner.) Search3 (Hit but not a winner.) Search4 (Miss on this device.) AI04690 Note: 1. 2. 3. 4. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0]. Each bit in LHO[1:0] is the same logical signal. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0]. Each bit in BHO[2:0] is the same logical signal. 58/159 M7040N Figure 39. Timing Diagram for Devices Below the Winning Device in Block Number 2 Cycle 2 Cycle 4 Cycle 6 Cycle 8 Cycle 10 Cycle 1 Cycle 3 Cycle 5 Cycle 7 Cycle 9 CLK2X PHS_L CMDV Search1 Search3 01 Search2 01 01 Search4 CMD[1:0] 01 CMD[10:2] A BABABAB DQ D1 D2 D3 D4 (LHI[6:0])(1) LHO[1:0](2) (BHI[2:0])(3) BHO[2:0](4) SADR[23:0] CE_L ALE_L WE_L OE_L SSV SSF 0 0 0 0 z z z z z z z Search1 (Miss on this device.) CFG = 0000000000000000, HLAT = 001, TLSZ = 10, LRAM = 0, LDEV = 0 Search2 (Miss on this device.) Search3 (Miss on this device.) Search4 (Miss on this device.) AI04691 Note: 1. 2. 3. 4. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0]. Each bit in LHO[1:0] is the same logical signal. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0]. Each bit in BHO[2:0] is the same logical signal. 59/159 M7040N Figure 40. Timing Diagram for Devices Above the Winning Device in Block Number 3 Cycle 2 Cycle 4 Cycle 6 Cycle 8 Cycle 10 Cycle 1 Cycle 3 Cycle 5 Cycle 7 Cycle 9 CLK2X PHS_L CMDV Search1 Search3 01 Search2 01 01 Search4 CMD[1:0] 01 CMD[10:2] A BABABAB DQ D1 0 0 D2 D3 D4 (LHI[6:0])(1) LHO[1:0](2) (BHI[2:0])(3) BHO[2:0](4) SADR[23:0] CE_L ALE_L WE_L OE_L SSV SSF 0 0 z z z z z z z Search1 (Miss on this device.) Search2 (Miss on this device.) CFG = 0000000000000000, HLAT = 001, TLSZ = 10, LRAM = 0, LDEV = 0 Search3 (Miss on this device.) Search4 (Miss on this device.) AI04692 Note: 1. 2. 3. 4. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0]. Each bit in LHO[1:0] is the same logical signal. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0]. Each bit in BHO[2:0] is the same logical signal. 60/159 M7040N Figure 41. Timing Diagram for the Globally Winning Device in Block Number 3 Cycle 2 Cycle 4 Cycle 6 Cycle 8 Cycle 10 Cycle 1 Cycle 3 Cycle 5 Cycle 7 Cycle 9 CLK2X PHS_L CMDV Search1 Search3 01 Search2 01 01 Search4 CMD[1:0] 01 CMD[10:2] A BABABAB DQ D1 0 D2 D3 D4 (LHI[6:0])(1) LHO[1:0](2) (BHI[2:0])(3) BHO[2:0](4) 0 0 0 z z 0 z 0 z z z SADR[23:0] CE_L ALE_L WE_L OE_L SSV SSF A1 z z z z Search1 (Global winner.) 1 z 1 1 z z CFG = 0000000000000000, HLAT = 001, TLSZ = 10, LRAM = 0, LDEV = 0 Search2 (Hit but not a global winner.) Search3 (Miss on this device.) Search4 (Miss on this device.) AI04693 Note: 1. 2. 3. 4. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0]. Each bit in LHO[1:0] is the same logical signal. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0]. Each bit in BHO[2:0] is the same logical signal. 61/159 M7040N Figure 42. Timing Diagram for Devices Below the Winning Device in Block Number 3 (except Device 30 - the Last Device) Cycle 2 Cycle 4 Cycle 6 Cycle 8 Cycle 10 Cycle 1 Cycle 3 Cycle 5 Cycle 7 Cycle 9 CLK2X PHS_L CMDV Search1 Search3 01 Search2 01 01 Search4 CMD[1:0] 01 CMD[10:2] A BABABAB DQ D1 D2 D3 D4 (LHI[6:0])(1) LHO[1:0](2) (BHI[2:0])(3) BHO[2:0](4) SADR[23:0] CE_L ALE_L WE_L OE_L SSV SSF 0 0 0 0 z z z z z z z Search1 (Miss on this device.) CFG = 0000000000000000, HLAT = 001, TLSZ = 10, LRAM = 0, LDEV = 0 Search2 (Miss on this device.) Search3 (Miss on this device.) Search4 (Miss on this device.) AI04694 Note: 1. 2. 3. 4. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0]. Each bit in LHO[1:0] is the same logical signal. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0]. Each bit in BHO[2:0] is the same logical signal. 62/159 M7040N Figure 43. Timing Diagram for Device 6 in Block Number 3 (Device 30 in Depth-Cascaded Table) Cycle 2 Cycle 4 Cycle 6 Cycle 8 Cycle 10 Cycle 1 Cycle 3 Cycle 5 Cycle 7 Cycle 9 CLK2X PHS_L CMDV Search1 Search3 01 Search2 01 01 Search4 CMD[1:0] 01 CMD[10:2] A BABABAB DQ D1 D2 D3 D4 (LHI[6:0])(1) LHO[1:0](2) (BHI[2:0])(3) BHO[2:0](4) 0 0 0 0 z z z SADR[23:0] CE_L ALE_L WE_L OE_L SSV SSF 0 Search1 (Hit on some device above.) 1 0 0 0 0 0 0 1 z z z 1 0 CFG = 0000000000000000, HLAT = 001, TLSZ = 10, LRAM = 1, LDEV = 1 Search2 (Hit on some device above.) Search3 (Hit on some device Search4 (Global miss; above.) this device default driver.) AI04695 Note: 1. 2. 3. 4. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0]. Each bit in LHO[1:0] is the same logical signal. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0]. Each bit in BHO[2:0] is the same logical signal. 63/159 M7040N Table 32. Latency of SEARCH from Instruction to SRAM Access Cycle # of devices 1 (TLSZ = 00) 1-8 (TLSZ = 01) 1-31 (TLSZ = 10) Max Table Size 64K x 72-bit 512K x 72-bit 1984K x 72-bit Latency in CLK Cycles 4 5 6 Table 33. Shift of SSF and SSV from SADR HLAT 000 001 010 011 100 101 110 111 Number of CLK Cycles 0 1 2 3 4 5 6 7 144-bit Configuration with Single Device The hardware diagram for this search subsystem is shown in Figure 44. Figure 45, page 66 shows the timing diagram for a SEARCH command in the 144-bit-configured table (CFG = 0101010101010101) consisting of a single device for one set of parameters. This illustration assumes that the host ASIC has programmed TLSZ to '00,' HLAT to '001,' LRAM to '1,' and LDEV to '1.' The following is the operation sequence for a single 144-bit SEARCH command (refer to COMMAND CODES AND PARAMETERS, page 30). - Cycle A: The host ASIC drives the CMDV high and applies SEARCH command code ('10') to CMD[1:0] signals. {CMD[10],CMD[5:3]} signals must be driven with the index to the GMR pair for use in this SEARCH operation. CMD[8:6] signals must be driven with the same bits that will be driven on SADR[23:21] by this device if it has a hit. DQ[71:0] must be driven with the 72bit data ([143:72]) to be compared against all even locations. The CMD[2] signal must be driven to logic '0.' - Cycle B: The host ASIC continues to drive the CMDV high and applies the command code of SEARCH command ('10') on CMD[1:0]. CMD[5:2] must be driven by the index of the comparand register pair for storing the 144-bit word presented on the DQ Bus during Cycles A and B. CMD[8:6] signals must be driven with the index of the SSR that will be used for storing the address of the matching entry and Hit Flag (see SEARCH-Successful Registers (SSR[0:7]), page 24). The DQ[71:0] is driven with 72-bit data ([71:0]), compared to all odd locations. Note: For 144-bit searches, the host ASIC must supply two distinct 72-bit data words on DQ[71:0] during Cycles A and B. The evennumbered GMR of the pair specified by the GMR Index is used for masking the word in Cycle A. The odd-numbered GMR of the pair specified by the GMR Index is used for masking the word in Cycle B. 64/159 M7040N The logical 144-bit search operation is shown in Figure 46, page 67. The entire table of 144-bit entries is compared to a 144-bit word K (presented on the DQ Bus in Cycles A and B of the command) using the GMR and the local mask bits. The GMR is the 144-bit word specified by the even and odd global mask pair selected by the GMR Index in the command's Cycle A. The 144-bit word K (presented on the DQ Bus in Cycles A and B of the command) is also stored in both even and odd comparand register pairs selected by the Comparand Register Index in the command's Cycle B. The two comparand registers can subsequently be used by the LEARN command with the even comparand register stored in an even location, and the odd comparand register stored in an adjacent odd location. The word K (presented on the DQ Bus in Cycles A and B of the command) is compared with each entry in the table starting at location "0." The first matching entry's location address, "L," is the winning address that is driven as part of the SRAM address on the SADR[23:0] lines (see SRAM ADDRESSING, page 128). Note: The matching address is always going to an even address for a 144-bit SEARCH. The SEARCH command is a pipelined operation that executes searches at half the rate of the frequency of CLK2X for 144-bit searches in x144configured tables. The latency of SADR, CE_L, ALE_L, WE_L, SSV, and SSF from the 144-bit SEARCH command cycle (two CLK2X cycles) is shown in Table 34, page 67. For a single device in the table with TLSZ = 00, the latency of the SEARCH from command to SRAM access cycle is 4. In addition, SSV and SSF shift further to the right for different values of HLAT, as specified in Table 35, page 67. Figure 44. Hardware Diagram for a Table with 1 Device BHI[2:0] 6 5 4 3 LHI 2 1 0 DQ[71:0] CMDV, CMD[10:0] SSF, SSV BHO[2:0] LHO[1] LHO[0] M7040 SRAM AI04698 65/159 M7040N Figure 45. Timing Diagram for a 144-bit SEARCH for 1 Device Cycle 2 Cycle 4 Cycle 6 Cycle 8 Cycle 10 Cycle 1 Cycle 3 Cycle 5 Cycle 7 Cycle 9 CLK2X PHS_L CMDV Search1 Search3 01 Search2 01 01 Search4 CMD[1:0] 01 CMD[10:2] A B A B A B A B DQ A B D1 A B A B A D4 B D2 D3 SADR[23:0] CE_L A1 A3 1 0 1 0 1 ALE_L WE_L 1 0 1 0 1 1 0 1 0 1 0 1 0 1 0 OE_L SSV SSF 0 1 0 0 1 0 1 0 Search1 Search3 Hit Hit Search4 Search2 Miss Miss CFG = 0101010101010101, HLAT = 001, TLSZ = 00, LRAM = 1, LDEV = 1 AI04697 66/159 M7040N Figure 46. x144 Table with One Device 143 GMR K Location 143 address 0 1 2 3 Even A Odd B 0 0 71 0 Comparand Register (even) A Comparand Register (odd) B L (First matching entry) 32766 CFG = 0101010101010101 (144-bit Configuration) AI04699 Table 34. Latency of SEARCH from Instruction to SRAM Access Cycle, 144-bit # of devices 1 (TLSZ = 00) 1-8 (TLSZ = 01) 1-31 (TLSZ = 10) Max Table Size 32K x 144-bit 256K x 144-bit 992K x 144-bit Latency in CLK Cycles 4 5 6 Table 35. Shift of SSF and SSV from SADR HLAT 000 001 010 011 100 101 110 111 Number of CLK Cycles 0 1 2 3 4 5 6 7 67/159 M7040N 144-bit Search on Tables Configured as x144 Using Up to Eight M7040N Devices and B. CMD[8:6] signals must be driven with the The hardware diagram of the search subsystem of eight devices is shown in Figure 47, page 69. The SSR Index that will be used for storing the adfollowing are parameters programmed into the dress of the matching entry and the Hit Flag eight devices: (see SEARCH-Successful Registers (SSR[0:7]), page 24). The DQ[71:0] is driven - First seven devices (devices 0-6): with 72-bit data ([71:0]) compared against all CFG = 0101010101010101, TLSZ = 01, odd locations. HLAT = 010, LRAM = 0, and LDEV = 0. The logical 144-bit search operation is shown in - Eighth device (device 7): Figure 48, page 70. The entire table (eight devices CFG = 0101010101010101, TLSZ = 01, of 144-bit entries) is compared to a 144-bit word K (presented on the DQ Bus in Cycles A and B of the HLAT = 010, LRAM = 1, and LDEV = 1. command) using the GMR and local mask bits. Note: All eight devices must be programmed with The GMR is the 144-bit word specified by the even the same value of TLSZ and HLAT. Only the last and odd global mask pair selected by the GMR Indevice in the table must be programmed with dex in the command's Cycle A. LRAM = 1 and LDEV = 1 (Device 7 in this case). The 144-bit word K (presented on the DQ Bus in All other upstream devices must be programmed Cycles A and B of the command) is also stored in with LRAM = 0 and LDEV = 0 (Devices 0 through the even and odd comparand registers specified 6 in this case). by the Comparand Register Index in the comFigure 49, page 71 shows the timing diagram for a mand's Cycle B. In x144 configurations, the even SEARCH command in the 144-bit-configured taand odd comparand registers can subsequently ble of eight devices for Device 0. Figure 50, page be used by the LEARN command in only one of 72 shows the timing diagram for a SEARCH comthe devices (the first non-full device). The word K mand in the 144-bit-configured table consisting of (presented on the DQ Bus in Cycles A and B of the eight devices for Device 1. Figure 51, page 73 command) is compared to each entry in the table shows the timing diagram for a SEARCH comstarting at location "0." The first matching entry's mand in the 144-bit configured table consisting of location, "L," is the winning address that is driven eight devices for Device 7 (the last device in this as part of the SRAM address on the SADR[23:0] specific table). For these timing diagrams, four lines (see SRAM ADDRESSING, page 128). The 144-bit searches are performed sequentially, and global winning device will drive the bus in a specifthe following HIT/MISS assumptions were made ic cycle. On global miss cycles the device with (see Table 36) LRAM = 1 (the default driving device for the SRAM The following is the sequence of operation for a Bus) and LDEV = 1 (the default driving device for single 144-bit SEARCH command (see COMSSF and SSV signals) will be the default driver for MAND CODES AND PARAMETERS, page 30). such missed cycles. - Cycle A: The host ASIC drives CMDV high and Note: During 144-bit searches of 144-bit-configapplies SEARCH command code ('10') on ured tables, the search hit will always be at an CMD[1:0] signals. {CMD[10],CMD[5:3]} signals even address. must be driven with the index to the GMR pair The SEARCH command is a pipelined operation for use in this SEARCH operation. CMD[8:6] and executes a search at half the rate of the fresignals must be driven with the same bits that quency of CLK2X for 144-bit searches in x144will be driven by this device on SADR[23:21] if it configured tables. The latency of SADR, CE_L, has a hit. DQ[71:0] must be driven with the 72ALE_L, WE_L, SSV, and SSF from the 144-bit bit data ([143:72]) in order to be compared SEARCH command cycle (two CLK2X cycles) is against all even locations. The CMD[2] signal shown in Table 37, page 74. must be driven to a logic '0.' For one to eight devices in the table and - Cycle B: The host ASIC continues to drive TLSZ = 01, the latency of a SEARCH from comCMDV high and to apply the command code for mand to SRAM access cycle is 5. In addition, SSV SEARCH command ('10') on CMD[1:0]. and SSF shift further to the right for different valCMD[5:2] must be driven by the index of the ues of HLAT as specified in Table 38, page 74. comparand register pair for storing the 144-bit word presented on the DQ Bus during Cycles A 68/159 M7040N Table 36. Hit/Miss Assumption Search Number Device 0 Device 1 Device 2-6 Device 7 1 Hit Miss Miss Miss 2 Miss Hit Miss Miss 3 Hit Hit Miss Hit 4 Miss Miss Miss Hit Figure 47. Hardware Diagram for a Table with Eight Devices SRAM BHI[2:0] LHO[1] 6 5 4 M7040 #0 3 LHI 2 1 0 LHO[0] SSF, SSV BHI[2:0] LHO[1] M7040 #1 6 5 4 3 LHI 2 1 LHO[0] 0 DQ[71:0] CMDV CMD[10:0] BHI[2:0] LHO[1] 6 5 4 3 2 LHI LHO[0] 1 0 M7040 #2 BHI[2:0] LHO[1] 6 5 4 M7040 #3 3 LHI LHO[0] 2 1 0 BHI[2:0] 6 5 4 M7040 #4 32 LHI 1 0 LHO[0] BHI[2:0] 3 2 1 LHI 0 6 M7040 #5 5 4 LHI LHO[0] BHI[2:0] 3 2 1 LHI 0 6 M7040 #6 5 4 LHI LHO[0] BHI[2:0] 3 2 1 LHI 0 6 M7040 #7 5 LHI 4 BHO[0] BHO[1] BHO[0] BHO[1] BHO[2] BHO[2] LHO[1] LHO[0] AI04679 69/159 M7040N Figure 48. x144 Table with Eight Devices 143 Must be the same in each of the eight devices GMR K Even A Odd B 0 71 0 Location 143 address 0 1 2 3 0 Comparand Register (even) A Comparand Register (odd) B L (First matching entry) 262142 Will be the same in each of the eight devices CFG = 0101010101010101 (144-bit Configuration) AI04701 70/159 M7040N Timing Diagrams for x144 Using Up to Eight M7040N Devices Figure 49. Timing Diagram for 144-bit SEARCH for Device Number 0 Cycle 2 Cycle 4 Cycle 6 Cycle 8 Cycle 10 Cycle 1 Cycle 3 Cycle 5 Cycle 7 Cycle 9 CLK2X PHS_L CMDV Search1 Search3 01 Search2 01 01 Search4 CMD[1:0] 01 CMD[10:2] A B A B A B A B DQ (LHI[6:0])(1) LHO[1:0](2) SADR[23:0] CE_L z z z 0 A B D1 A B A D3 B A D4 B D2 A1 z z A3 z z 0 z 0 z z z z Search1 (This device is the global winner.) z 0 z 0 z ALE_L WE_L OE_L SSV SSF 1 1 1 1 z z 1 1 z z CFG = 0101010101010101, HLAT = 010, TLSZ = 01, LRAM = 0, LDEV = 0 Search2 (Miss on this device.) Search3 (This device is the global winner.) Search4 (Miss on this device.) AI04664 Note: 1. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0]. 2. Each bit in LHO[1:0] is the same logical signal. 71/159 M7040N Figure 50. Timing Diagram for 144-bit SEARCH for Device Number 1 Cycle 2 Cycle 4 Cycle 6 Cycle 8 Cycle 10 Cycle 1 Cycle 3 Cycle 5 Cycle 7 Cycle 9 CLK2X PHS_L CMDV Search1 Search3 01 Search2 01 01 Search4 A B A B CMD[1:0] 01 CMD[10:2] A B A B DQ A B A B A B A D4 B D1 D2 D3 (LHI[6:0])(1) LHO[1:0](2) SADR[23:0] CE_L ALE_L z z 0 z 0 z z z z Search1 (Miss on this device.) z z A2 z WE_L OE_L SSV SSF 1 1 1 z z CFG = 0000000000000000, HLAT = 010, TLSZ = 01, LRAM = 0, LDEV = 0 Search2 (This device is global winner.) Search3 (Local winner but not global winner.) Search4 (Miss on this device.) AI04663 Note: 1. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0]. 2. Each bit in LHO[1:0] is the same logical signal. 72/159 M7040N Figure 51. Timing Diagram for 144-bit SEARCH for Device Number 7 (Last Device) Cycle 2 Cycle 4 Cycle 6 Cycle 8 Cycle 10 Cycle 1 Cycle 3 Cycle 5 Cycle 7 Cycle 9 CLK2X PHS_L CMDV Search1 Search3 01 Search2 01 01 Search4 A B A B CMD[1:0] 01 CMD[10:2] A B A B DQ A B D1 A B A B A D4 B D2 D3 (LHI[6:0])(1) LHO[1:0](2) SADR[23:0] CE_L ALE_L WE_L OE_L SSV SSF 0 0 z A4 z z z 0 0 1 0 0 0 Search1 (Miss on this device.) 1 1 z 1 z 0 0 CFG = 0101010101010101, HLAT = 010, TLSZ = 01, LRAM = 1, LDEV = 1 Search2 (Miss on this device.) Search3 (Local winner but not global winner.) Search4 (Global winner.) AI04700 Note: 1. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0]. 2. Each bit in LHO[1:0] is the same logical signal. 73/159 M7040N Table 37. Latency of SEARCH from Instruction to SRAM Access Cycle, 144-bit # of devices 1 (TLSZ = 00) 1-8 (TLSZ = 01) 1-31 (TLSZ = 10) Max Table Size 32K x 144-bit 256K x 144-bit 992K x 144-bit Latency in CLK Cycles 4 5 6 Table 38. Shift of SSF and SSV from SADR HLAT 000 001 010 011 100 101 110 111 Number of CLK Cycles 0 1 2 3 4 5 6 7 144-bit Search on Tables Configured as x144 Using Up to 31 M7040N Devices The hardware diagram of the search subsystem of one device with a matching entry in each of the 31 devices is shown in Figure 52, page 76. Each blocks. Figure 55, page 79 shows the timing diaof the four blocks in the diagram represents a gram for a SEARCH command in the 144-bit-conblock of eight M7040N devices (except the last, figured table (31 devices) for each of the eight which has seven devices).The diagram for a block devices in Block 0. Figure 56, page 80 shows the of eight devices is shown in Figure 53, page 77. timing diagram for SEARCH command in the Following are the parameters programmed into 72-bit-configured table (31 devices) for all the dethe 31 devices. vices in Block 1 above the winning device in that block. Figure 57, page 81 shows the timing diaFirst thirty devices (devices 0-29): gram for the globally winning device (the final winCFG = 0101010101010101, TLSZ = 10, ner within its own block and all blocks) in Block 1. HLAT = 001, LRAM = 0, and LDEV = 0. Figure 58, page 82 shows the timing diagram for Thirty-first device (device 30): all the devices below the globally winning device in CFG = 0101010101010101, TLSZ = 10, Block 1. Figure 59, page 83, Figure 60, page 84, HLAT = 001, LRAM = 1, and LDEV = 1. and Figure 61, page 85 respectively show the timNote: All 31 devices must be programmed with the ing diagrams of the devices above globally winsame value of TLSZ and HLAT. Only the last dening device, the globally winning device and vice in the table must be programmed with devices below the globally winning device for LRAM = 1 and LDEV = 1 (Device 30 in this case). Block 2. Figure 62, page 86, Figure 63, page 87, All other upstream devices must be programmed Figure 64, page 88, and Figure 65, page 89 rewith LRAM = 0 and LDEV = 0 (Devices 0 through spectively show the timing diagrams of the devices 29 in this case). above the globally winning device, the globally winning device, and devices below the globally The timing diagrams referred to in this paragraph winning device except the last device (Device 30), reference the HIT/MISS assumptions defined in and the last device (Device 30) for Block 3. Table 39, page 75. For the purpose of illustrating timings, it is further assumed that the there is only 74/159 M7040N The following is the sequence of operation for a single 144-bit SEARCH command (see COMMAND CODES AND PARAMETERS, page 30). - Cycle A: The host ASIC drives the CMDV high and applies SEARCH command code ('10') on CMD[1:0] signals. {CMD[10],CMD[5:3]} signals must be driven with the index to the GMR pair for use in this SEARCH operation. CMD[8:6] signals must be driven with the bits that will be driven on SADR[23:21] by this device if it has a hit. DQ[71:0] must be driven with the 72-bit data ([143:72]) in order to be compared against all even locations. The CMD[2] signal must be driven to logic '0.' - Cycle B: The host ASIC continues to drive the CMDV high and to apply SEARCH command code ('10') on CMD[1:0]. CMD[5:2] must be driven by the index of the comparand register pair for storing the 144-bit word presented on the DQ Bus during Cycles A and B. CMD[8:6] signals must be driven with the index of the SSR that will be used for storing the address of the matching entry and the Hit Flag (see SEARCHSuccessful Registers (SSR[0:7]), page 24). The DQ[71:0] is driven with 72-bit data ([71:0]) to be compared against all odd locations. The logical 144-bit search operation is as shown in Figure 54, page 78. The entire table of 31 devices (consisting of 144-bit entries) is compared against a 144-bit word K that is presented on the DQ Bus in Cycles A and B of the command using the GMR and local mask bits. The GMR is the 144-bit word specified by the even and odd global mask pair selected by the GMR Index in the command's Cycle A. The 144-bit word K that is presented on the DQ Bus in Cycles A and B of the command is also stored in the even and odd comparand registers specified by the Comparand Register Index in the command's Cycle B. In x144 configurations, the even and odd comparand registers can subsequently be used by the LEARN command in only the first non-full device. Note: The LEARN command is supported for only one of the blocks consisting of up to eight devices in a depth-cascaded table of more than one block. Table 39. Hit/Miss Assumption Search Number Block 0 Block 1 Block 2 Block 3 1 Miss Miss Miss Hit 2 Miss Miss Hit Hit 3 Miss Hit Hit Miss 4 Miss Miss Miss Miss The word K that is presented on the DQ Bus in Cycles A and B of the command is compared with each entry in the table starting at location "0." The first matching entry's location address, "L," is the winning address that is driven as part of the SRAM address on the SADR[23:0] lines (see SRAM ADDRESSING, page 128). The global winning device will drive the bus in a specific cycle. On global miss cycles the device with LRAM = 1 (the default driving device for the SRAM bus) and LDEV = 1 (the default driving device for SSF and SSV signals) will be the default driver for such missed cycles. Note: During 144-bit searches of 144-bit-configured tables, the search hit will always be at an even address. The SEARCH command is a pipelined operation. It executes a search at half the rate of the frequency of CLK2X for 144-bit searches in x144-configured tables. The latency of SADR, CE_L, ALE_L, WE_L, SSV, and SSF from the 144-bit SEARCH command cycle (two CLK2X cycles) is shown in Table 40, page 90. The latency of a search from command to the SRAM access cycle is 6 for 1-31 devices in the table and where TLSZ = 10. In addition, SSV and SSF shift further to the right for different values of HLAT, as specified in Table 41, page 90. The 144-bit SEARCH operation is pipelined and executes as follows: - Four cycles from the SEARCH command, each of the devices knows the outcome internal to it for that operation. - In the fifth cycle after the SEARCH command, the devices in a block (being less than or equal to eight devices resolving the winner within them using the LHI[6:0] and LHO[1:0] signalling mechanism) arbitrate for a winner amongst them. - In the sixth cycle after the SEARCH command, the blocks (of devices) resolve the winning block through the BHI[2:0] and BHO[2:0] signalling mechanism. The winning device in the winning block is the global winning device for a SEARCH operation. 75/159 M7040N Figure 52. Hardware Diagram for a Table with 31 Devices BHI[2] BHI[1] BHI[0] GND SSF, SSV BHO[2] Block of 8 M7040s, Block 0 (Devices 0-7) BHO[1] BHO[0] SRAM BHI[2] BHI[1] BHI[0] GND Block of 8 M7040s, Block 1 (Devices 8-15) BHO[2] BHO[1] BHO[0] BHI[2] BHI[1] BHI[0] GND Block of 8 M7040s, Block 2 (Devices 16-23) BHO[2] BHO[1] BHO[0] BHI[2] BHI[1] BHI[0] DQ[71:0] CMD[10:0], CMDV Block of 7 M7040s, Block 3 (Devices 24-30) BHO[2] BHO[1] BHO[0] AI04684 76/159 M7040N Figure 53. Hardware Diagram for a Block of Up to Eight Devices BHI[2:0] BHI[2:0] LHO[1] 6 5 4 SRAM M7040 #0 3 LHI 2 1 0 LHO[0] BHI[2:0] DQ[71:0] CMDV CMD[10:0] BHI[2:0] LHO[1] M7040 #1 6 5 4 3 LHI 2 1 0 LHO[0] 6 LHO[1] 5 4 SSV, SSF M7040 #2 3 2 1 LHI LHO[0] 0 BHI[2:0] LHO[1] 6 5 4 M7040 #3 3 2 LHI LHO[0] 1 0 BHI[2:0] 6 5 4 M7040 #4 32 LHI 1 0 LHO[0] BHI[2:0] 3 2 1 LHI 0 6 M7040 #5 5 4 LHI LHO[0] BHI[2:0] 3 2 1 LHI 0 6 M7040 #6 5 4 LHI LHO[0] BHI[2:0] 3 2 1 LHI 0 6 M7040 #7 5 LHI 4 BHO[0] BHO[1] BHO[0] BHO[1] BHO[2] BHO[2] LHO[1] LHO[0] AI04685 77/159 M7040N Figure 54. x144 Table with 31 Devices 143 Must be the same in each of the 31 devices GMR K Even A Odd B 0 71 0 Location 143 address 0 1 2 3 0 Comparand Register (even) A Comparand Register (odd) B L (First matching entry) 1015806 Will be the same in each of the 31 devices CFG = 0101010101010101 (144-bit Configuration) AI04702 78/159 M7040N Timing Diagrams for x144 Using Up to 31 M7040N Devices Figure 55. Timing Diagram for Each Device in Block Number 0 (Miss on Each Device) Cycle 2 Cycle 4 Cycle 6 Cycle 8 Cycle 10 Cycle 1 Cycle 3 Cycle 5 Cycle 7 Cycle 9 CLK2X PHS_L CMDV Search1 Search3 01 Search2 01 01 Search4 A B A B CMD[1:0] 01 CMD[10:2] A B A B DQ (LHI[6:0])(1) LHO[1:0](2) (BHI[2:0])(3) BHO[2:0](4) SADR[23:0] CE_L ALE_L WE_L OE_L SSV SSF 0 0 0 0 z z z z z z z A B A B A B A D4 B D1 D2 D3 CFG = 0101010101010101, HLAT = 001, TLSZ = 10, LRAM = 0, LDEV = 0 Search1 (Miss on this device.) Search2 (Miss on this device.) Search3 (Miss on this device.) Search4 (Miss on this device.) AI04703 Note: 1. 2. 3. 4. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0]. Each bit in LHO[1:0] is the same logical signal. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0]. Each bit in BHO[2:0] is the same logical signal. 79/159 M7040N Figure 56. Timing Diagram for Each Device Above the Winning Device in Block Number 1 Cycle 2 Cycle 4 Cycle 6 Cycle 8 Cycle 10 Cycle 1 Cycle 3 Cycle 5 Cycle 7 Cycle 9 CLK2X PHS_L CMDV Search1 Search3 01 Search2 01 01 Search4 A B A B CMD[1:0] 01 CMD[10:2] A B A B DQ (LHI[6:0]) (1) 0 0 0 0 z z z z z z z A B A B A B A D4 B D1 D2 D3 LHO[1:0](2) (BHI[2:0])(3) BHO[2:0](4) SADR[23:0] CE_L ALE_L WE_L OE_L SSV SSF CFG = 0101010101010101, HLAT = 001, TLSZ = 10, LRAM = 0, LDEV = 0 Search1 (Miss on this device.) Search2 (Miss on this device.) Search3 (Miss on this device.) Search4 (Miss on this device.) AI04703 Note: 1. 2. 3. 4. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0]. Each bit in LHO[1:0] is the same logical signal. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0]. Each bit in BHO[2:0] is the same logical signal. 80/159 M7040N Figure 57. Timing Diagram for the Globally Winning Device in Block Number 1 Cycle 2 Cycle 4 Cycle 6 Cycle 8 Cycle 10 Cycle 1 Cycle 3 Cycle 5 Cycle 7 Cycle 9 CLK2X PHS_L CMDV Search1 Search3 01 Search2 01 01 Search4 CMD[1:0] 01 CMD[10:2] A BABABAB DQ A 0 BABABAB D1 D2 D3 D4 (LHI[6:0])(1) LHO[1:0](2) (BHI[2:0])(3) BHO[2:0](4) SADR[23:0] CE_L ALE_L WE_L OE_L SSV SSF 0 0 0 z z 0 z 0 z z z z Search1 (Miss on this device.) Search2 (Miss on this device.) Search3 (This device global winner.) Search4 (Miss on this device.) 1 1 z z 1 z z z z A3 CFG = 0101010101010101, HLAT = 001, TLSZ = 10, LRAM = 0, LDEV = 0 AI04704 Note: 1. 2. 3. 4. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0]. Each bit in LHO[1:0] is the same logical signal. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0]. Each bit in BHO[2:0] is the same logical signal. 81/159 M7040N Figure 58. Timing Diagram for Devices Below the Winning Device in Block Number 1 Cycle 2 Cycle 4 Cycle 6 Cycle 8 Cycle 10 Cycle 1 Cycle 3 Cycle 5 Cycle 7 Cycle 9 CLK2X PHS_L CMDV Search1 Search3 01 Search2 01 01 Search4 CMD[1:0] 01 CMD[10:2] A BABABAB DQ A BABABAB D2 D3 D4 D1 (LHI[6:0])(1) LHO[1:0](2) (BHI[2:0])(3) BHO[2:0](4) SADR[23:0] CE_L ALE_L WE_L OE_L SSV SSF 0 0 0 0 z z z z z z z Search1 (Miss on this device.) Search2 (Miss on this device.) CFG = 0101010101010101, HLAT = 001, TLSZ = 10, LRAM = 0, LDEV = 0 Search3 (Miss on this device.) Search4 (Miss on this device.) AI04705 Note: 1. 2. 3. 4. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0]. Each bit in LHO[1:0] is the same logical signal. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0]. Each bit in BHO[2:0] is the same logical signal. 82/159 M7040N Figure 59. Timing Diagram for Devices Above the Winning Device in Block Number 2 Cycle 2 Cycle 4 Cycle 6 Cycle 8 Cycle 10 Cycle 1 Cycle 3 Cycle 5 Cycle 7 Cycle 9 CLK2X PHS_L CMDV Search1 Search3 01 Search2 01 01 Search4 CMD[1:0] 01 CMD[10:2] A BABABAB DQ A 0 0 BABABAB D2 D3 D4 D1 (LHI[6:0])(1) LHO[1:0](2) (BHI[2:0])(3) BHO[2:0](4) SADR[23:0] CE_L ALE_L WE_L OE_L SSV SSF 0 0 z z z z z z z Search1 (Miss on this device.) Search2 (Miss on this device.) CFG = 0101010101010101, HLAT = 001, TLSZ = 10, LRAM = 0, LDEV = 0 Search3 (Miss on this device.) Search4 (Miss on this device.) AI04706 Note: 1. 2. 3. 4. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0]. Each bit in LHO[1:0] is the same logical signal. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0]. Each bit in BHO[2:0] is the same logical signal. 83/159 M7040N Figure 60. Timing Diagram for the Globally Winning Device in Block Number 2 Cycle 2 Cycle 4 Cycle 6 Cycle 8 Cycle 10 Cycle 1 Cycle 3 Cycle 5 Cycle 7 Cycle 9 CLK2X PHS_L CMDV Search1 Search3 01 Search2 01 01 Search4 CMD[1:0] 01 CMD[10:2] A BABABAB DQ A BABABAB D1 D2 D3 D4 (LHI[6:0])(1) LHO[1:0](2) (BHI[2:0])(3) BHO[2:0](4) 0 0 0 0 z z 0 z 0 z z z SADR[23:0] CE_L ALE_L WE_L OE_L SSV SSF A2 z z z z Search1 (Miss on this device.) 1 z 1 1 z z CFG = 0101010101010101, HLAT = 001, TLSZ = 10, LRAM = 0, LDEV = 0 Search2 (Global winner.) Search3 (Hit but not a winner.) Search4 (Miss on this device.) AI04707 Note: 1. 2. 3. 4. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0]. Each bit in LHO[1:0] is the same logical signal. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0]. Each bit in BHO[2:0] is the same logical signal. 84/159 M7040N Figure 61. Timing Diagram for Devices Below the Winning Device in Block Number 2 Cycle 2 Cycle 4 Cycle 6 Cycle 8 Cycle 10 Cycle 1 Cycle 3 Cycle 5 Cycle 7 Cycle 9 CLK2X PHS_L CMDV Search1 Search3 01 Search2 01 01 Search4 CMD[1:0] 01 CMD[10:2] A BABABAB DQ A BABABAB D1 D2 D3 D4 (LHI[6:0])(1) LHO[1:0](2) (BHI[2:0])(3) BHO[2:0](4) SADR[23:0] CE_L ALE_L WE_L OE_L SSV SSF 0 0 0 0 z z z z z z z Search1 (Miss on this device.) CFG = 0101010101010101, HLAT = 001, TLSZ = 10, LRAM = 0, LDEV = 0 Search2 (Miss on this device.) Search3 (Miss on this device.) Search4 (Miss on this device.) AI04708 Note: 1. 2. 3. 4. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0]. Each bit in LHO[1:0] is the same logical signal. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0]. Each bit in BHO[2:0] is the same logical signal. 85/159 M7040N Figure 62. Timing Diagram for Devices Above the Winning Device in Block Number 3 Cycle 2 Cycle 4 Cycle 6 Cycle 8 Cycle 10 Cycle 1 Cycle 3 Cycle 5 Cycle 7 Cycle 9 CLK2X PHS_L CMDV Search1 Search3 01 Search2 01 01 Search4 CMD[1:0] 01 CMD[10:2] A BABABAB DQ A 0 0 BABABAB D2 D3 D4 D1 (LHI[6:0])(1) LHO[1:0](2) (BHI[2:0])(3) BHO[2:0](4) SADR[23:0] CE_L ALE_L WE_L OE_L SSV SSF 0 0 z z z z z z z Search1 (Miss on this device.) Search2 (Miss on this device.) CFG = 0101010101010101, HLAT = 001, TLSZ = 10, LRAM = 0, LDEV = 0 Search3 (Miss on this device.) Search4 (Miss on this device.) AI04709 Note: 1. 2. 3. 4. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0]. Each bit in LHO[1:0] is the same logical signal. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0]. Each bit in BHO[2:0] is the same logical signal. 86/159 M7040N Figure 63. Timing Diagram for the Globally Winning Device in Block Number 3 Cycle 2 Cycle 4 Cycle 6 Cycle 8 Cycle 10 Cycle 1 Cycle 3 Cycle 5 Cycle 7 Cycle 9 CLK2X PHS_L CMDV Search1 Search3 01 Search2 01 01 Search4 CMD[1:0] 01 CMD[10:2] A BABABAB DQ A 0 BABABAB D2 D3 D4 D1 (LHI[6:0])(1) LHO[1:0](2) (BHI[2:0])(3) BHO[2:0](4) 0 0 0 z z 0 z 0 z z z SADR[23:0] CE_L ALE_L WE_L OE_L SSV SSF A1 z z z z Search1 (Global winner.) 1 z 1 1 z z CFG = 0101010101010101, HLAT = 001, TLSZ = 10, LRAM = 0, LDEV = 0 Search2 (Hit but not a global winner.) Search3 (Miss on this device.) Search4 (Miss on this device.) AI04710 Note: 1. 2. 3. 4. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0]. Each bit in LHO[1:0] is the same logical signal. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0]. Each bit in BHO[2:0] is the same logical signal. 87/159 M7040N Figure 64. Timing Diagram for Devices Below the Winning Device in Block Number 3 (except Device 30 - the Last Device) Cycle 2 Cycle 4 Cycle 6 Cycle 8 Cycle 10 Cycle 1 Cycle 3 Cycle 5 Cycle 7 Cycle 9 CLK2X PHS_L CMDV Search1 Search3 01 Search2 01 01 Search4 CMD[1:0] 01 CMD[10:2] A BABABAB DQ A BABABAB D2 D3 D4 D1 (LHI[6:0])(1) LHO[1:0](2) (BHI[2:0])(3) BHO[2:0](4) SADR[23:0] CE_L ALE_L WE_L OE_L SSV SSF 0 0 0 0 z z z z z z z Search1 (Miss on this device.) CFG = 0101010101010101, HLAT = 001, TLSZ = 10, LRAM = 0, LDEV = 0 Search2 (Miss on this device.) Search3 (Miss on this device.) Search4 (Miss on this device.) AI04711 Note: 1. 2. 3. 4. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0]. Each bit in LHO[1:0] is the same logical signal. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0]. Each bit in BHO[2:0] is the same logical signal. 88/159 M7040N Figure 65. Timing Diagram for Device 6 in Block Number 3 (Device 30 in Depth-Cascaded Table) Cycle 2 Cycle 4 Cycle 6 Cycle 8 Cycle 10 Cycle 1 Cycle 3 Cycle 5 Cycle 7 Cycle 9 CLK2X PHS_L CMDV Search1 Search3 01 Search2 01 01 Search4 CMD[1:0] 01 CMD[10:2] A BABABAB DQ A BABABAB D2 D3 D4 D1 (LHI[6:0])(1) LHO[1:0](2) (BHI[2:0])(3) BHO[2:0](4) 0 0 0 0 z z z SADR[23:0] CE_L ALE_L WE_L OE_L SSV SSF 0 0 1 0 0 1 z 0 z z 0 Search1 (Hit on some device above.) 0 1 0 CFG = 0101010101010101, HLAT = 001, TLSZ = 10, LRAM = 1, LDEV = 1 Search2 (Hit on some device above.) Search3 (Hit on some device Search4 (Global miss; above.) this device default driver.) AI04712 Note: 1. 2. 3. 4. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0]. Each bit in LHO[1:0] is the same logical signal. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0]. Each bit in BHO[2:0] is the same logical signal. 89/159 M7040N Table 40. Latency of SEARCH from Instruction to SRAM Access Cycle, 144-bit # of devices 1 (TLSZ = 00) 1-8 (TLSZ = 01) 1-31 (TLSZ = 10) Max Table Size 32K x 144-bit 256K x 144-bit 992K x 144-bit Latency in CLK Cycles 4 5 6 Table 41. Shift of SSF and SSV from SADR HLAT 000 001 010 011 100 101 110 111 Number of CLK Cycles 0 1 2 3 4 5 6 7 288-bit SEARCH on Tables Configured as x288 Using a Single M7040N Device The hardware diagram for this search subsystem - Cycle C: The host ASIC drives the CMDV high is shown in Figure 66, page 91. Figure 67, page 92 and applies SEARCH command code ('10') on shows the timing diagram for a SEARCH comCMD[1:0] signals. {CMD[10],CMD[5:3]} signals mand in the 288-bit-configured table (CFG = must be driven with the index to the GMR pair 1010101010101010) consisting of a single device used for bits [143:0] of the data being searched. for one set of parameters: TLSZ = '00,' HLAT = CMD[8:6] signals must be driven with the bits '001,' LRAM = '1,' and LDEV = '1.' that will be driven on SADR[23:21] by this device if it has a hit. DQ[71:0] must be driven with The following is the sequence of operation for a the 72-bit data ([143:72]) to be compared to all single 144-bit SEARCH command (also refer to locations "2" in the four 72-bits-word page. The COMMAND CODES AND PARAMETERS, page CMD[2] signal must be driven to logic '0.' 30). - Cycle D: The host ASIC continues to drive the - Cycle A: The host ASIC drives the CMDV high CMDV high and applies SEARCH command and applies SEARCH command code ('10') on code ('10') on CMD[1:0]. CMD[8:6] signals must CMD[1:0] signals. {CMD[10],CMD[5:3]} signals be driven with the index of the SSR that will be must be driven with the index to the GMR pair used for storing the address of the matching enused for bits [287:144] of the data being try and the Hit Flag (see SEARCH-Successful searched. DQ[71:0] must be driven with the 72Registers (SSR[0:7]), page 24). The DQ[71:0] is bit data ([287:216]) to be compared to all locadriven with the 72-bit data ([71:0]) to be comtions "0" in the four 72-bits-word page. The pared to all locations "3" in the four 72-bits-word CMD[2] signal must be driven to logic "1." page. CMD[5:2] is ignored because the LEARN Note: CMD[2] = 1 signals that the search is a Instruction is not supported for x288 tables. x288-bit search. CMD[8:3] in this cycle is igNote: For 288-bit searches, the host ASIC must nored. supply four distinct 72-bit data words on - Cycle B: The host ASIC continues to drive the DQ[71:0] during Cycles A, B, C, and D. The CMDV high and continues to apply the comGMR Index in Cycle A selects a pair of GMRs mand code of SEARCH command ('10') on that apply to DQ data in Cycles A and B. The CMD[1:0]. The DQ[71:0] is driven with the 72-bit GMR Index in Cycle C selects a pair of GMRs data ([215:144]) to be compared to all locations that apply to DQ data in Cycles C and D. "1" in the four 72-bits-word page. 90/159 M7040N The logical 288-bit SEARCH operation is shown in Figure 68, page 93. The entire table of 288-bit entries is compared to a 288-bit word K that is presented on the DQ Bus in Cycles A, B, C, and D of the command using the GMR and local mask bits. The GMR is the 288-bit word specified by the two pairs of GMRs selected by the GMR Indexes in the command's Cycles A and C. The 288-bit word K that is presented on the DQ Bus in Cycles A, B, C, and D of the command is compared with each entry in the table starting at location "0." The first matching entry's location address, "L," is the winning address that is driven as part of the SRAM address on SADR[23:0] lines (see SRAM ADDRESSING, page 128). Note: The matching address is always going to be location "0" in a four-entry page for a 288-bit SEARCH (two LSBs of the matching index will be '00'). The SEARCH command is a pipelined operation and executes at one-fourth the rate of the frequency of CLK2X for 288-bit searches in x288-configured tables. The latency of SADR, CE_L, ALE_L, WE_L, SSV, and SSF from the 288-bit SEARCH command (measured in CLK cycles) from the CLK2X cycle that contains the C and D Cycles is shown in Table 42, page 93. The latency of a SEARCH from command to SRAM access cycle is 4 for only a single device in the table and TLSZ = 00. In addition, SSV and SSF shift further to the right for different values of HLAT, as specified in Table 43, page 93. Figure 66. Hardware Diagram for a Table with One Device BHI[2:0] 6 5 4 3 LHI 2 1 0 DQ[71:0] CMDV, CMD[10:0] SSF, SSV BHO[2:0] LHO[1] LHO[0] M7040 SRAM AI04698 91/159 M7040N Figure 67. Timing Diagram for 288-bit SEARCH (One Device) Cycle 2 Cycle 4 Cycle 6 Cycle 8 Cycle 10 Cycle 1 Cycle 3 Cycle 5 Cycle 7 Cycle 9 CLK2X PHS_L CMDV Search1 Search2 01 CMD[1:0] 01 CMD[2] CMD[10:2] A B A B A B A B DQ A B C D A B D2 C D D1 SADR[23:0] CE_L A1 1 0 1 ALE_L WE_L 1 0 1 1 0 1 0 1 0 OE_L SSV SSF 0 1 0 1 0 0 1 0 Search1 Hit Search2 Miss AI04713 CFG = 1010101010101010, HLAT = 001, TLSZ = 00, LRAM = 1, LDEV = 1 92/159 M7040N Figure 68. x288 Table with One Device 287 GMR K Location 287 address 0 4 8 12 0 A 1 B 2 C 3 D 0 0 L (First matching entry) 16380 CFG = 1010101010101010 (288-bit Configuration) AI04714 Table 42. Latency of SEARCH from Cycles C and D to SRAM Access Cycle # of devices 1 (TLSZ = 00) 2-8 (TLSZ = 01) 2-31 (TLSZ = 10) Max Table Size 16K x 288-bit 128K x 288-bit 496K x 288-bit Latency in CLK Cycles 4 5 6 Table 43. Shift of SSF and SSV from SADR HLAT 000 001 010 011 100 101 110 111 Number of CLK Cycles 0 1 2 3 4 5 6 7 93/159 M7040N 288-bit SEARCH on Tables x288-configured Using Up to Eight M7040N Devices against all locations "1" in the four 72-bits-word The hardware diagram of the search subsystem of page. eight devices is shown in Figure 69, page 96. The following are the parameters programmed in the - Cycle C: The host ASIC drives the CMDV high eight devices. and applies SEARCH command code ('10') on CMD[1:0] signals. {CMD[10],CMD[5:3]} signals - First seven devices (devices 0-6): must be driven with the index to the GMR pair CFG = 1010101010101010, TLSZ = 01, used for bits [143:0] of the data being searched. HLAT = 000, LRAM = 0, and LDEV = 0. CMD[8:6] signals must be driven with the bits - Eighth device (device 7): that will be driven on SADR[23:21] by this deCFG = 1010101010101010, TLSZ = 01, vice if it has a hit. DQ[71:0] must be driven with the 72-bit data ([143:72]) to be compared HLAT = 000, LRAM = 1, and LDEV = 1. against all locations "2" in the four 72-bits-word Note: All eight devices must be programmed with page. The CMD[2] signal must be driven to logic the same value of TLSZ and HLAT. Only the last '0.' device in the table must be programmed with - Cycle D: The host ASIC continues to drive the LRAM = 1 and LDEV = 1 (Device 7 in this case). CMDV high and applies SEARCH command All other upstream devices must be programmed code ('10') on CMD[1:0]. CMD[8:6] signals must with LRAM = 0 and LDEV = 0 (Devices 0 through be driven with the index of the SSR that will be 6 in this case). used for storing the address of the matching enFigure 71, page 98 shows the timing diagram for a try and the Hit Flag (see SEARCH-Successful SEARCH command in the 288-bit-configured taRegisters (SSR[0:7]), page 24). The DQ[71:0] is ble of eight devices for Device 0. Figure 72, page driven with the 72-bit data ([71:0]) to be com99 shows the timing diagram for a SEARCH compared to all locations "3" in the four 72-bits-word mand in the 288-bit-configured table of eight depage. CMD[5:2] is ignored because the LEARN vices for Device 1. Figure 73, page 100 shows the Instruction is not supported for x288 tables. timing diagram for a SEARCH command in the Note: For 288-bit searches, the host ASIC must 288-bit-configured table of eight devices for Desupply four distinct 72-bit data words on vice 7 (the last device in this specific table). For DQ[71:0] during Cycles A, B, C, and D. The these timing diagrams three 288-bit searches are GMR Index in Cycle A selects a pair of GMRs in performed sequentially. The following HIT/MISS each of the eight devices that apply to DQ data assumptions were made as shown in Table 44, in Cycles A and B. The GMR Index in Cycle C page 95. selects a pair of GMRs in each of the eight deThe following is the sequence of operation for a vices that apply to DQ data in Cycles C and D. single 288-bit SEARCH command (also COMThe logical 288-bit SEARCH operation is shown in MAND CODES AND PARAMETERS, page 30). Figure 70, page 97. The entire table of 288-bit en- Cycle A: The host ASIC drives the CMDV high tries is compared to a 288-bit word K that is preand applies SEARCH command code ('10') on sented on the DQ Bus in Cycles A, B, C, and D of CMD[1:0] signals. {CMD[10],CMD[5:3]} signals the command using the GMR and the local mask must be driven with the index to the GMR pair bits. The GMR is the 288-bit word specified by the used for bits [287:144] of the data being two pairs of GMRs selected by the GMR Indexes searched in this operation. DQ[71:0] must be in the command's Cycles A and C in each of the driven with the 72-bit data ([287:216]) to be eight devices. The 288-bit word K that is presented compared against all locations "0" in the fouron the DQ Bus in Cycles A, B, C, and D of the comword, 72-bit page. The CMD[2] signal must be mand is compared to each entry in the table startdriven to logic '1.' ing at location "0." The first matching entry's Note: CMD[2] = 1 signals that the search is a location address, "L," is the winning address that is 288-bit search. CMD[8:3] in this cycle is igdriven as part of the SRAM address on the nored. SADR[23:0] lines (see SRAM ADDRESSING, page 128). - Cycle B: The host ASIC continues to drive the CMDV high and applies SEARCH command Note: The matching address is always going to be code ('10') on CMD[1:0]. The DQ[71:0] is driven a location "0" in a four-entry page for 288-bit with the 72-bit data ([215:144]) to be compared SEARCH (two LSBs of the matching index will be '00'). 94/159 M7040N The SEARCH command is a pipelined operation and executes search at one-fourth the rate of the frequency of CLK2X for 288-bit searches in x288configured tables. The latency of SADR, CE_L, ALE_L, WE_L, SSV, and SSF from the 288-bit SEARCH command (measured in CLK cycles) from the CLK2X cycle that contains the C and D Cycles is shown in Table 45, page 101. The latency of search from command to SRAM access cycle is 5 for only a single device in the table and TLSZ = 01. In addition, SSV and SSF shift further to the right for different values of HLAT, as specified in Table 46, page 101. Table 44. Hit/Miss Assumption Search Number Device 0 Device 1 Device 2-6 Device 7 1 Hit Miss Miss Miss 2 Miss Hit Miss Miss 3 Miss Miss Miss Miss 95/159 M7040N Figure 69. Hardware Diagram for a Table with Eight Devices SRAM BHI[2:0] LHO[1] 6 5 4 M7040 #0 3 LHI 2 1 0 LHO[0] SSF, SSV BHI[2:0] LHO[1] M7040 #1 6 5 4 3 LHI 2 1 LHO[0] 0 DQ[71:0] CMDV CMD[10:0] BHI[2:0] LHO[1] 6 5 4 3 2 LHI LHO[0] 1 0 M7040 #2 BHI[2:0] LHO[1] 6 5 4 M7040 #3 3 LHI LHO[0] 2 1 0 BHI[2:0] 6 5 4 M7040 #4 32 LHI 1 0 LHO[0] BHI[2:0] 3 2 1 LHI 0 6 M7040 #5 5 4 LHI LHO[0] BHI[2:0] 3 2 1 LHI 0 6 M7040 #6 5 4 LHI LHO[0] BHI[2:0] 3 2 1 LHI 0 6 M7040 #7 5 LHI 4 BHO[0] BHO[1] BHO[0] BHO[1] BHO[2] BHO[2] LHO[1] LHO[0] AI04679 96/159 M7040N Figure 70. x288 Table with Eight Devices 287 GMR K 0 A 1 B 2 C 3 D 0 Must be the same in each of eight devices Location 287 address 0 4 8 12 0 L (First matching entry) 131068 CFG = 1010101010101010 (288-bit Configuration) AI04718 97/159 M7040N Timing Diagrams for x288-configured Using Up to Eight M7040N Devices Figure 71. Timing Diagram for 288-bit SEARCH for Device Number 0 Cycle 2 Cycle 4 Cycle 6 Cycle 8 Cycle 10 Cycle 1 Cycle 3 Cycle 5 Cycle 7 Cycle 9 CLK2X PHS_L CMDV Search1 Search2 01 Search3 01 CMD[1:0] CMD[2] 01 CMD[10:2] A BA B A B A B A BA B DQ (LHI[6:0])(1) LHO[1:0](2) SADR[23:0] CE_L z z z 0 A BC D1 DA BC D2 DA BC D3 D A1 z z 0 z 0 z z z z Search1 (This device is the global winner.) z z z z ALE_L WE_L OE_L SSV SSF 1 1 1 CFG = 1010101010101010, HLAT = 000, TLSZ = 01, LRAM = 0, LDEV = 0 Search2 (Miss on this device.) Search3 (Miss on this device.) AI04715 Note: 1. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0]. 2. Each bit in LHO[1:0] is the same logical signal. 98/159 M7040N Figure 72. Timing Diagram for 288-bit SEARCH for Device Number 1 Cycle 2 Cycle 4 Cycle 6 Cycle 8 Cycle 10 Cycle 1 Cycle 3 Cycle 5 Cycle 7 Cycle 9 CLK2X PHS_L CMDV Search1 Search2 01 Search3 01 CMD[1:0] CMD[2] CMD[10:2] 01 A BA B A B A B A BA B DQ A BC D1 DA BC D2 DA BC D3 D (LHI[6:0])(1) LHO[1:0](2) SADR[23:0] CE_L z z z 0 z 0 z z z z z z z z A2 ALE_L WE_L OE_L SSV SSF 1 1 1 Search1 (Miss on this device.) CFG = 1010101010101010, HLAT = 000, TLSZ = 01, LRAM = 0, LDEV = 0 Search2 (This device is global winner.) Search3 (Miss on this device.) AI04716 Note: 1. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0]. 2. Each bit in LHO[1:0] is the same logical signal. 99/159 M7040N Figure 73. Timing Diagram for 288-bit SEARCH for Device Number 7 (Last Device) Cycle 2 Cycle 4 Cycle 6 Cycle 8 Cycle 10 Cycle 1 Cycle 3 Cycle 5 Cycle 7 Cycle 9 CLK2X PHS_L CMDV Search1 Search2 01 Search3 01 CMD[1:0] CMD[2] CMD[10:2] 01 A BA B A B A B A BA B DQ A BC D1 DA BC D2 DA BC D3 D (LHI[6:0])(1) LHO[1:0](2) SADR[23:0] z A2 z 0 z z 0 z 0 z 0 z 0 0 z 0 z 0 z 0 0 1 CE_L ALE_L WE_L OE_L 1 SSV SSF 0 1 CFG = 1010101010101010, HLAT = 000, TLSZ = 01, LRAM = 1, LDEV = 1 Search1 (Miss on this device.) Search2 (Miss on this device.) Search3 (Global miss.) AI04717 Note: 1. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0]. 2. Each bit in LHO[1:0] is the same logical signal. 100/159 M7040N Table 45. Latency of SEARCH from Cycles C and D to SRAM Access Cycle, 288-bit # of devices 1 (TLSZ = 00) 1-8 (TLSZ = 01) 1-31 (TLSZ = 10) Max Table Size 16K x 288-bit 128K x 288-bit 496K x 288-bit Latency in CLK Cycles 4 5 6 Table 46. Shift of SSF and SSV from SADR HLAT 000 001 010 011 100 101 110 111 Number of CLK Cycles 0 1 2 3 4 5 6 7 288-bit Search on Tables Configured as x288 Using Up to 31 M7040N Devices The hardware diagram of the search subsystem of the timings, it is further assumed that there is only 31 devices is shown in Figure 74, page 103. Each one device with the matching entry in each block. of the four blocks in the diagram represents a Figure 77, page 106 shows the timing diagram for block of eight M7040N devices, except the last a SEARCH command in the 288-bit-configured tawhich has seven devices.The diagram for a block ble consisting of 31 devices for each of the eight of eight devices is shown in Figure 75, page 104. devices in Block 0. Figure 78, page 107 shows the The following are the parameters programmed timing diagram for a SEARCH command in the into the 31 devices. 288-bit-configured table of 31 devices for all devices above the winning device in Block 1. Figure 79, - First thirty devices (devices 0-29): page 108 shows the timing diagram for the globalCFG = 1010101010101010, TLSZ = 10, ly winning device (the final winner within its own HLAT = 000, LRAM = 0, and LDEV = 0. and all blocks) in Block 1. Figure 80, page 109 shows the timing diagram for all the devices below - Thirty-first device (device 30): the globally winning device in Block 1. Figure 81, CFG = 1010101010101010, TLSZ = 10, page 110, Figure 82, page 111, and Figure 83, HLAT = 000, LRAM = 1, and LDEV = 1. page 112, respectively, show the timing diagrams Note: All 31 devices must be programmed with the of the devices above the globally winning device, same value of TLSZ and HLAT. Only the last dethe globally winning device, and the devices below vice in the table must be programmed with the globally winning device for Block 2. Figure 84, LRAM = 1 and LDEV = 1 (Device 30 in this case). page 113, Figure 85, page 114, Figure 86, page All other upstream devices must be programmed 115, and Figure 87, page 116, respectively, show with LRAM = 0 and LDEV = 0 (Devices 0 through the timing diagrams of the device above the glo29 in this case). bally winning device, the globally winning device, the devices below the globally winning device (exThe timing diagrams referred to in this paragraph cept Device 30), and last device (Device 30) for reference the HIT/MISS assumptions defined in Block 3. Table 47, page 103. For the purpose of illustrating 101/159 M7040N The following is the sequence of operation for a single 288-bit SEARCH command (see COMMAND CODES AND PARAMETERS, page 30). - Cycle A: The host ASIC drives the CMDV high and applies SEARCH command code ('10') on CMD[1:0] signals. {CMD[10],CMD[5:3]} signals must be driven with the index to the GMR pair used for bits [287:144] of the data being searched. DQ[71:0] must be driven with the 72bit data ([287:216])to be compared to all locations "0" in the four 72-bit-word page. The CMD[2] signal must be driven to logic '1.' Note: CMD[2] = 1 signals that the search is a x288-bit search. CMD[8:6] is ignored in this cycle. - Cycle B: The host ASIC continues to drive the CMDV high and applies SEARCH command ('10') on CMD[1:0]. The DQ[71:0] is driven with the 72-bit data ([215:144]) to be compared to all locations '1' in the four 72-bits-word page. - Cycle C: The host ASIC drives the CMDV high and applies SEARCH command code ('10') on CMD[1:0] signals. {CMD[10],CMD[5:3]} signals must be driven with the index to the GMR pair used for the bits [143:0] of the data being searched. CMD[8:6] signals must be driven with the bits that will be driven by this device on SADR[23:21] if it has a hit. DQ[71:0] must be driven with the 72-bit data ([143:72]) to be compared to all locations "2" in the four 72-bit-word page. The CMD[2] signal must be driven to logic '0.' - Cycle D: The host ASIC continues to drive the CMDV high and continues to apply SEARCH command code ('10') on CMD[1:0]. CMD[8:6] signals must be driven with the index of the SSR that will be used for storing the address of the matching entry and the Hit Flag (see SEARCHSuccessful Registers (SSR[0:7]), page 24). The DQ[71:0] is driven with the 72-bit data ([71:0]) to be compared to all locations "3" in the four 72bit-word page. CMD[5:2] is ignored because the LEARN Instruction is not supported for x288 tables. Note: For 288-bit searches, the host ASIC must supply four distinct 72-bit data words on DQ[71:0] during Cycles A, B, C, and D. The GMR Index in Cycle A selects a pair of GMRs in each of the 31 devices that apply to DQ data in Cycles A and B. The GMR Index in Cycle C selects a pair of GMRs in each of the 31 devices that apply to DQ data in Cycles C and D. The logical 288-bit SEARCH operation is as shown in Figure 76, page 105. The entire table of 288-bit entries is compared to a 288-bit word K that is presented on the DQ Bus in Cycles A, B, C, and D of the command using the GMR and local mask bits. The GMR is the 288-bit word specified by the two pairs of GMRs selected by the GMR Indexes in the command's Cycles A and C in each of the 31 devices. The 288-bit word K that is presented on the DQ Bus in Cycles A, B, C, and D of the command is compared to each entry in the table starting at location "0." The first matching entry's location address, "L," is the winning address that is driven as part of the SRAM address on the SADR[23:0] lines (see SRAM ADDRESSING, page 128). Note: The matching address is always going to be location "0" in a four-entry page for 288-bit search (two LSBs of the matching index will be '00'). The SEARCH command is a pipelined operation and executes a search at one-fourth the rate of the frequency of CLK2X for 288-bit searches in x288configured tables. The latency of SADR, CE_L, ALE_L, WE_L, SSV, and SSF from the 288-bit SEARCH command (measured in CLK cycles) from the CLK2X cycle that contains Cycles C and D shown in Table 48, page 117. The latency of a SEARCH from command to SRAM access cycle is 6 for only a single device in the table and TLSZ = 10. In addition, SSV and SSF shift further to the right for different values of HLAT, as specified in Table 49, page 117 The 288-bit SEARCH operation is pipelined and executes as follows: - Four cycles from the last cycle of the SEARCH command each of the devices knows the outcome internal to it for that operation. - In the fifth cycle from the SEARCH command, the devices in a block (which is less than or equal to eight devices resolving the winner within them using an LHI[6:0] and LHO[1:0] signalling mechanism) arbitrate for a winner. - In the sixth cycle after the SEARCH command, the blocks of devices resolve the winning block through a BHI[2:0] and BHO[2:0] signalling mechanism. The winning device within the winning block is the global winning device for the SEARCH operation. 102/159 M7040N Table 47. Hit/Miss Assumption Search Number Block 0 Block 1 Block 2 Block 3 1 Miss Miss Miss Hit 2 Miss Miss Hit Hit 3 Miss Hit Hit Miss Figure 74. Hardware Diagram for a Table with 31 Devices BHI[2] BHI[1] BHI[0] GND SSF, SSV BHO[2] Block of 8 M7040s, Block 0 (Devices 0-7) BHO[1] BHO[0] SRAM BHI[2] BHI[1] BHI[0] GND Block of 8 M7040s, Block 1 (Devices 8-15) BHO[2] BHO[1] BHO[0] BHI[2] BHI[1] BHI[0] GND Block of 8 M7040s, Block 2 (Devices 16-23) BHO[2] BHO[1] BHO[0] BHI[2] BHI[1] BHI[0] DQ[71:0] CMD[10:0], CMDV Block of 7 M7040s, Block 3 (Devices 24-30) BHO[2] BHO[1] BHO[0] AI04684 103/159 M7040N Figure 75. Hardware Diagram for a Block of Up to Eight Devices BHI[2:0] BHI[2:0] LHO[1] 6 5 4 SRAM M7040 #0 3 LHI 2 1 0 LHO[0] BHI[2:0] DQ[71:0] CMDV CMD[10:0] BHI[2:0] LHO[1] M7040 #1 6 5 4 3 LHI 2 1 0 LHO[0] 6 LHO[1] 5 4 SSV, SSF M7040 #2 3 2 1 LHI LHO[0] 0 BHI[2:0] LHO[1] 6 5 4 M7040 #3 3 2 LHI LHO[0] 1 0 BHI[2:0] 6 5 4 M7040 #4 32 LHI 1 0 LHO[0] BHI[2:0] 3 2 1 LHI 0 6 M7040 #5 5 4 LHI LHO[0] BHI[2:0] 3 2 1 LHI 0 6 M7040 #6 5 4 LHI LHO[0] BHI[2:0] 3 2 1 LHI 0 6 M7040 #7 5 LHI 4 BHO[0] BHO[1] BHO[0] BHO[1] BHO[2] BHO[2] LHO[1] LHO[0] AI04685 104/159 M7040N Figure 76. x288 Table with 31 Devices 287 GMR K 0 A 1 B 2 C 3 D 0 Must be the same in each of 31 devices Location 287 address 0 4 8 12 0 L (First matching entry) 507900 CFG = 1010101010101010 (288-bit Configuration) AI04729 105/159 M7040N Timing Diagrams for x288 Using Up to 31 M7040N Devices Figure 77. Timing Diagram for Each Device in Block Number 0 (Miss on Each Device) Cycle 2 Cycle 4 Cycle 6 Cycle 8 Cycle 10 Cycle 1 Cycle 3 Cycle 5 Cycle 7 Cycle 9 CLK2X PHS_L CMDV Search1 Search2 01 Search3 01 CMD[1:0] CMD[2] 01 CMD[10:2] A BA B A B A B A BA B DQ (LHI[6:0])(1) LHO[1:0](2) (BHI[2:0]) BHO[1:0] (3) (4) 0 0 0 0 z z z z z z z A BC D1 DA BC D2 DA BC D3 D SADR[23:0] CE_L ALE_L WE_L OE_L SSV SSF CFG = 1010101010101010, HLAT = 000, TLSZ = 10, LRAM = 0, LDEV = 0 Search1 (Miss on this device.) Search2 (Miss on this device.) Search3 (Miss on this device.) AI04719 Note: 1. 2. 3. 4. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0]. Each bit in LHO[1:0] is the same logical signal. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0]. Each bit in BHO[2:0] is the same logical signal. 106/159 M7040N Figure 78. Timing Diagram for Each Device Above the Winning Device in Block Number 1 Cycle 2 Cycle 4 Cycle 6 Cycle 8 Cycle 10 Cycle 1 Cycle 3 Cycle 5 Cycle 7 Cycle 9 CLK2X PHS_L CMDV Search1 Search2 01 Search3 01 CMD[1:0] CMD[2] 01 CMD[10:2] A BA B A B A B A BA B DQ (LHI[6:0])(1) LHO[1:0] (2) (3) 0 0 0 0 z z z z z z z A BC D1 DA B C D2 DA BC D3 D (BHI[2:0]) BHO[1:0] (4) SADR[23:0] CE_L ALE_L WE_L OE_L SSV SSF CFG = 1010101010101010, HLAT = 000, TLSZ = 10, LRAM = 0, LDEV = 0 Search1 (Miss on this device.) Search2 (Miss on this device.) Search3 (Miss on this device.) AI04719 Note: 1. 2. 3. 4. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0]. Each bit in LHO[1:0] is the same logical signal. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0]. Each bit in BHO[2:0] is the same logical signal. 107/159 M7040N Figure 79. Timing Diagram for the Globally Winning Device in Block Number 1 Cycle 2 Cycle 4 Cycle 6 Cycle 8 Cycle 10 Cycle 1 Cycle 3 Cycle 5 Cycle 7 Cycle 9 CLK2X PHS_L CMDV Search1 Search2 01 Search3 01 CMD[1:0] CMD[2] CMD[10:2] DQ (LHI[6:0])(1) LHO[1:0](2) (BHI[2:0]) (3) 0 A 01 BA B A B A B A BA B A BC D1 DA BC D2 DA BC D3 D 0 0 BHO[1:0](4) SADR[23:0] CE_L ALE_L WE_L OE_L SSV SSF 0 z z 0 z 0 A3 z z z z 1 1 1 Search1 (Miss on this device.) CFG = 1010101010101010, HLAT = 000, TLSZ = 10, LRAM = 0, LDEV = 0 Search2 (Miss on this device.) Search3 (This device global winner.) AI04720 Note: 1. 2. 3. 4. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0]. Each bit in LHO[1:0] is the same logical signal. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0]. Each bit in BHO[2:0] is the same logical signal. 108/159 M7040N Figure 80. Timing Diagram for Devices Below the Winning Device in Block Number 1 Cycle 2 Cycle 4 Cycle 6 Cycle 8 Cycle 10 Cycle 1 Cycle 3 Cycle 5 Cycle 7 Cycle 9 CLK2X PHS_L CMDV Search1 Search2 01 Search3 01 CMD[1:0] CMD[2] CMD[10:2] DQ A 01 BA B A B A B A BA B A BC D1 DA BC D2 DA BC D3 D (LHI[6:0]) (1) (2) 0 0 0 LHO[1:0] (BHI[2:0])(3) BHO[1:0](4) SADR[23:0] CE_L ALE_L WE_L OE_L SSV SSF 0 z z z z z z z Search1 (Miss on this device.) CFG = 1010101010101010, HLAT = 000, TLSZ = 10, LRAM = 0, LDEV = 0 Search2 (Miss on this device.) Search3 (Miss on this device.) AI04721 Note: 1. 2. 3. 4. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0]. Each bit in LHO[1:0] is the same logical signal. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0]. Each bit in BHO[2:0] is the same logical signal. 109/159 M7040N Figure 81. Timing Diagram for Devices Above the Winning Device in Block Number 2 Cycle 2 Cycle 4 Cycle 6 Cycle 8 Cycle 10 Cycle 1 Cycle 3 Cycle 5 Cycle 7 Cycle 9 CLK2X PHS_L CMDV Search1 Search2 01 Search3 01 CMD[1:0] CMD[2] CMD[10:2] DQ (LHI[6:0])(1) LHO[1:0](2) (BHI[2:0])(3) BHO[1:0] (4) 0 0 A 01 BA B A B A B A BA B A BC D1 DA BC D2 DA BC D3 D 0 0 z z z z z z z Search1 (Miss on this device.) SADR[23:0] CE_L ALE_L WE_L OE_L SSV SSF CFG = 1010101010101010, HLAT = 000, TLSZ = 10, LRAM = 0, LDEV = 0 Search2 (Miss on this device.) Search3 (Miss on this device; hit in Block 0 or 1.) AI04722 Note: 1. 2. 3. 4. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0]. Each bit in LHO[1:0] is the same logical signal. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0]. Each bit in BHO[2:0] is the same logical signal. 110/159 M7040N Figure 82. Timing Diagram for the Globally Winning Device in Block Number 2 Cycle 2 Cycle 4 Cycle 6 Cycle 8 Cycle 10 Cycle 1 Cycle 3 Cycle 5 Cycle 7 Cycle 9 CLK2X PHS_L CMDV Search1 Search2 01 Search3 01 CMD[1:0] CMD[2] CMD[10:2] DQ (LHI[6:0])(1) LHO[1:0](2) (BHI[2:0])(3) BHO[1:0](4) SADR[23:0] CE_L ALE_L WE_L OE_L SSV SSF 0 A 01 BA B A B A B A BA B A BC D1 DA BC D2 DA BC D3 D 0 0 0 z z z z 0 z 0 z z z z Search1 (Miss on this device.) 1 1 z z z 1 z z z z A2 CFG = 1010101010101010, HLAT = 000, TLSZ = 10, LRAM = 0, LDEV = 0 Search2 (Global winner.) Search3 (Hit but not a winner.) AI04723 Note: 1. 2. 3. 4. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0]. Each bit in LHO[1:0] is the same logical signal. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0]. Each bit in BHO[2:0] is the same logical signal. 111/159 M7040N Figure 83. Timing Diagram for Devices Below the Winning Device in Block Number 2 Cycle 2 Cycle 4 Cycle 6 Cycle 8 Cycle 10 Cycle 1 Cycle 3 Cycle 5 Cycle 7 Cycle 9 CLK2X PHS_L CMDV Search1 Search2 01 Search3 01 CMD[1:0] CMD[2] CMD[10:2] DQ A 01 BA B A B A B A BA B A BC D1 DA BC D2 DA BC D3 D (LHI[6:0])(1) LHO[1:0] (2) 0 0 (BHI[2:0])(3) BHO[1:0](4) SADR[23:0] CE_L ALE_L WE_L OE_L SSV SSF 0 0 z z z z z z z Search1 (Miss on this device.) CFG = 1010101010101010, HLAT = 000, TLSZ = 10, LRAM = 0, LDEV = 0 Search2 (Miss on this device.) Search3 (Miss on this device.) AI04724 Note: 1. 2. 3. 4. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0]. Each bit in LHO[1:0] is the same logical signal. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0]. Each bit in BHO[2:0] is the same logical signal. 112/159 M7040N Figure 84. Timing Diagram for Devices Above the Winning Device in Block Number 3 Cycle 2 Cycle 4 Cycle 6 Cycle 8 Cycle 10 Cycle 1 Cycle 3 Cycle 5 Cycle 7 Cycle 9 CLK2X PHS_L CMDV Search1 Search2 01 Search3 01 CMD[1:0] CMD[2] CMD[10:2] DQ (LHI[6:0]) (1) 0 0 A 01 BA B A B A B A BA B A BC D1 DA BC D2 DA BC D3 D LHO[1:0](2) (BHI[2:0])(3) BHO[1:0] (4) 0 0 z z z z z z z Search1 (Miss on this device.) SADR[23:0] CE_L ALE_L WE_L OE_L SSV SSF CFG = 1010101010101010, HLAT = 000, TLSZ = 10, LRAM = 0, LDEV = 0 Search2 (Miss on this device.) Search3 (Miss on this device.) AI04725 Note: 1. 2. 3. 4. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0]. Each bit in LHO[1:0] is the same logical signal. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0]. Each bit in BHO[2:0] is the same logical signal. 113/159 M7040N Figure 85. Timing Diagram for the Globally Winning Device in Block Number 3 Cycle 2 Cycle 4 Cycle 6 Cycle 8 Cycle 10 Cycle 1 Cycle 3 Cycle 5 Cycle 7 Cycle 9 CLK2X PHS_L CMDV Search1 Search2 01 Search3 01 CMD[1:0] CMD[2] CMD[10:2] DQ (LHI[6:0])(1) LHO[1:0](2) (BHI[2:0])(3) BHO[1:0] (4) 0 A 01 BA B A B A B A BA B A BC D1 DA BC D2 DA BC D3 D 0 0 0 z z 0 z 0 z z z SADR[23:0] CE_L ALE_L WE_L OE_L SSV SSF A1 z z z z Search1 (Global winner.) 1 z 1 1 z z CFG = 1010101010101010, HLAT = 000, TLSZ = 10, LRAM = 0, LDEV = 0 Search2 (Hit but not a global winner.) Search3 (Miss on this device.) AI04726 Note: 1. 2. 3. 4. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0]. Each bit in LHO[1:0] is the same logical signal. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0]. Each bit in BHO[2:0] is the same logical signal. 114/159 M7040N Figure 86. Timing Diagram for Devices Below the Winning Device in Block Number 3 (except Device 30 - the Last Device) Cycle 2 Cycle 4 Cycle 6 Cycle 8 Cycle 10 Cycle 1 Cycle 3 Cycle 5 Cycle 7 Cycle 9 CLK2X PHS_L CMDV Search1 Search2 01 Search3 01 CMD[1:0] CMD[2] CMD[10:2] DQ A 01 BA B A B A B A BA B A BC D1 DA BC D2 DA BC D3 D (LHI[6:0])(1) LHO[1:0] (2) 0 0 (BHI[2:0])(3) BHO[1:0](4) SADR[23:0] CE_L ALE_L WE_L OE_L SSV SSF 0 0 z z z z z z z Search1 (Miss on this device.) CFG = 1010101010101010, HLAT = 000, TLSZ = 10, LRAM = 0, LDEV = 0 Search2 (Miss on this device.) Search3 (Miss on this device.) AI04727 Note: 1. 2. 3. 4. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0]. Each bit in LHO[1:0] is the same logical signal. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0]. Each bit in BHO[2:0] is the same logical signal. 115/159 M7040N Figure 87. Timing Diagram of the Last Device in Block Number 3 (Device 30 in the Table) Cycle 2 Cycle 4 Cycle 6 Cycle 8 Cycle 10 Cycle 1 Cycle 3 Cycle 5 Cycle 7 Cycle 9 CLK2X PHS_L CMDV Search1 Search2 01 Search3 01 CMD[1:0] CMD[2] CMD[10:2] DQ |(LHI[6:0])(1) 0 A 01 BA B A B A B A BA B A BC D1 DA BC D2 DA BC D3 D LHO[1:0] (2) 0 |(BHI[2:0])(3) BHO[1:0](4) SADR[23:0] CE_L ALE_L WE_L OE_L SSV SSF 0 0 z z 0 z z z z z z z Search1 (Hit on some device above.) Search2 (Hit on some device above.) Search3 (Hit on some device above.) 0 z z 0 z 0 0 z z 0 z 0 z z 0 z z 1 1 CFG = 1010101010101010, HLAT = 000, TLSZ = 10, LRAM = 1, LDEV = 1 AI04728 Note: 1. 2. 3. 4. (LHI[6:0]) stands for the boolean 'OR' of the entire bus LHI[6:0]. Each bit in LHO[1:0] is the same logical signal. (BHI[2:0]) stands for the boolean 'OR' of the entire bus BHI[2:0]. Each bit in BHO[2:0] is the same logical signal. 116/159 M7040N Table 48. Latency of SEARCH from Cycles C and D to SRAM Access Cycle, 288-bit # of devices 1 (TLSZ = 00) 2-8 (TLSZ = 01) 2-31 (TLSZ = 10) Max Table Size 16K x 288-bit 128K x 288-bit 496K x 288-bit Latency in CLK Cycles 4 5 6 Table 49. Shift of SSF and SSV from SADR HLAT 000 001 010 011 100 101 110 111 Number of CLK Cycles 0 1 2 3 4 5 6 7 MIXED SEARCHES Tables Configured with Different Widths Using an M7040N with CFG_L LOW The sample operation shown is for a single device with CFG = 1010010100000000. It contains three tables of x72, x144, and x288 widths. The operation may be generalized to a block of 8-31 devices using four blocks; the timing and the pipeline operation is the same as described previously for fixed searches on a table of one-width-size. Figure 88, page 118 shows three sequential searches: - a 72-bit search on the table configured as x72; - a 144-bit search on a table configured as x144; and - a 288-bit search on the table configured as x288 bits that each results in a hit. Note: The DQ[71:70] will be '00' in both of the Cycles A and B of the x72-bit search (Search1). DQ[71:70] is '01' in both of the Cycles A and B of the x144-bit search (Search2). DQ[71:70] is '10' in all of the Cycles A, B, C, and D of the x288-bit search (Search 3). By having table designation bits, the M7040N enables the creation of many tables in a bank of search engines of different widths. Figure 89, page 119 shows the sample table. Two bits in each 72-bit entry will need to designated as the Table Number Bits. One example choice can be the '00' values for the table configured as x72, '01' values for tables configured as x144, and '10' values for tables configured as x288. For the above explanation, it is further assumed that bits [71:70] for each entry will be designed as these Table Designation Bits. Tables Configured to Different Widths using an M7040N with CFG_L HIGH Searches on tables of different widths using Table Designation Bits in the data array can be wasteful of these bits. In order to avoid wasting these bits and still support up to three tables of x72, x144, and x288, the CMD[2] and CMD[9] (in CFG_L high mode) in Cycle A of the command can be used as shown in Table 50, page 119. 117/159 M7040N Figure 88. Timing Diagram for Mixed SEARCH (One Device) Cycle 2 Cycle 4 Cycle 6 Cycle 8 Cycle 10 Cycle 1 Cycle 3 Cycle 5 Cycle 7 Cycle 9 CLK2X PHS_L CMDV Search1 Search3 01 Search2 01 CMD[1:0] 01 CMD[2] CMD[10:2] DQ A A BA BA B B D2 A A B A B D BC D3 D1 SADR[23:0] CE_L ALE_L WE_L 1 A1 A2 A3 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 1 0 0 1 1 0 0 OE_L 0 0 0 Search1 (x72 Hit) Search2 (x144 Hit) SSV SSF CFG = 1010101010101010, HLAT = 010, TLSZ = 00, LRAM = 1, LDEV = 1 Search3 (x288 Hit) AI04730 118/159 M7040N Figure 89. Multi-Width Configurations Example 72 32 K 8K 4K 144 288 CFG = 10 10 01 01 00 00 00 00 AI04731 Table 50. Searches with CFG_L Set HIGH CMD[9] 0 1 X X CMD[2] 0 0 1 0 SEARCH Search 72-bit-configured partitions only Search 144-bit-configured partitions only Cycles A and B for searching 288-bit-configured partitions Cycles C and D for searching 288-bit-configured partitions LRAM AND LDEV DESCRIPTION When search engines are cascaded using multiple M7040Ns, the SADR, CE_L, and WE_L (3-state signals) are all tied together. In order to eliminate external pull-up and pull-downs, one device in a bank is designated as the default driver. For nonSEARCH or non-LEARN cycles (see LEARN COMMAND in the section below) or search cycles with a global miss, the SADR, CE_L, and WE_L signals are driven by the device with the LRAM Bit set. Note: It is important that only one device in a bank of search engines that are cascaded have this bit set. Failure to do so will cause contention on SADR, CE_L, WE_L, and can potentially cause damage to the device(s). Similarly, when search engines using multiple M7040Ns are cascaded, SSF and SSV (also 3state signals) are tied together. In order to eliminate external pull-up and pull-downs, one device in a bank is designated as the default driver. For non-SEARCH cycles or SEARCH cycles with a global miss the SSF and SSV signals are driven by the device with the LDEV Bit set. Note: It is important that only one device in a bank of search engines that are cascaded together have this bit set. Failure to do so will cause contention on SSV and SSF and can potentially cause damage to the device(s). 119/159 M7040N LEARN COMMAND Bit [0] of each 72-bit data location specifies whether an entry in the database is occupied. If all the entries in a device are occupied, the device asserts FULO signal to inform the downstream devices that it is full. The result of this communication between depthcascaded devices determines the global FULL signal for the entire table. The FULL signal in the last device determines the fullness of the depthcascaded table. In a depth-cascaded table, only a single device will learn the entry through the application of a LEARN Instruction. The determination of which device is going to learn is based on the FULI and FULO signalling between the devices. The first non-full device learns the entry by storing the contents of the specified comparand registers to the location(s) pointed to by NFA. In a x72-configured table the LEARN command writes a single 72-bit location. In a x144-configured table the LEARN command writes the next even and odd 72-bit locations. In 144-bit mode, Bit[0] of the even and odd 72-bit locations is '0,' which indicates they are cascaded empty, or '1,' which indicates they are occupied. The global FULL signal indicates to the Table Controller (the host ASIC) that all entries within a block are occupied and that no more entries can be learned. The M7040N updates the signal after each WRITE or LEARN command to a data array. The LEARN command generates a WRITE cycle to the external SRAM, also using the NFA register as part of the SRAM address (see SRAM ADDRESSING, page 128). The LEARN command is supported on a single block containing up to eight devices if the table is configured either as a x72 or a x144. The LEARN command is not supported for x288-configured tables. LEARN is a pipelined operation and lasts for two CLK cycles, as shown in Figure 90, page 121 where TLSZ = 00, and Figure 91, page 122 and Figure 92, page 123 where TLSZ = 01 (which assume the device performing the LEARN operation is not the last device in the table and has its LRAM Bit set to '0.' Note: The OE_L for the device with the LRAM Bit set goes high for two cycles for each LEARN (one during the SRAM WRITE cycle, and one the cycle before). The latency of the SRAM WRITE cycle from the second cycle of the Instruction is shown in Table 51, page 123. The sequence of operation is as follows: - Cycle 1A: The host ASIC applies the LEARN Instruction on the CMD[1:0], using CMDV = 1. The CMD[5:2] field specifies the index of the comparand register pair that will be written in the data array in the 144-bit-configured table. For a LEARN in a 72-bit-configured table, the even-numbered comparands specified by this index will be written. CMD[8:6] carries the bits that will be driven on SADR[23:21] in the SRAM WRITE cycle. - Cycle 1B: The host ASIC continues to drive CMDV to '1,' CMD[1:0] to '11,' and CMD[5:2] with the comparand pair index. CMD[6] must be set to '0' if the LEARN is being performed on a 72-bit-configured table, and to '1' if the LEARN is being performed on a 144-bit-configured table. - Cycle 2: The host ASIC drives the CMDV to '0.' At the end of Cycle 2, a new instruction can begin. The latency of the SRAM WRITE is the same as the search to the SRAM READ Cycle. 120/159 M7040N Figure 90. Timing Diagram of LEARN: TLSZ = 00 Cycle 2 Cycle 4 Cycle 6 Cycle 8 Cycle 10 Cycle 1 Cycle 3 Cycle 5 Cycle 7 Cycle 9 CLK2X PHS_L CMDV CMD[1:0] Learn1 X Learn2 X Comp1 Comp2 X X CMD[10:2] 1A 1B DQ SADR[23:0] CE_L WE_L OE_L SSV SSF X X X X A1 0 0 z A2 0 0 1 1 1 1 1 0 0 0 0 TLSZ = 00, LRAM = 1, LDEV = 1 AI04732 121/159 M7040N Figure 91. Timing Diagram of LEARN: TLSZ = 01 (Except on the Last Device) Cycle 2 Cycle 4 Cycle 6 Cycle 8 Cycle 10 Cycle 1 Cycle 3 Cycle 5 Cycle 7 Cycle 9 CLK2X PHS_L CMDV CMD[1:0] Learn1 X Learn2 X Comp1 Comp2 X X CMD[10:2] 1A 1B DQ SADR[23:0] CE_L WE_L OE_L SSV SSF z X z z X X X z A1 0 z A2 0 0 z z 0 z z z TLSZ = 01, LRAM = 0, LDEV = 0 AI04733 122/159 M7040N Figure 92. Timing Diagram of LEARN on Device 7: TLSZ = 01 Cycle 2 Cycle 4 Cycle 6 Cycle 8 Cycle 10 Cycle 1 Cycle 3 Cycle 5 Cycle 7 Cycle 9 CLK2X PHS_L CMDV CMD[1:0] Learn1 X Learn2 X Comp1 Comp2 X X CMD[10:2] 1A 1B DQ SADR[23:0] CE_L WE_L OE_L SSV SSF X X X X z z z 1 1 1 z z 1 1 z z 1 1 0 0 0 0 TLSZ = 01, LRAM = 1, LDEV = 1 AI04734 Table 51. Latency of SRAM WRITE Cycle from Second Cycle of LEARN Instruction # of devices 1 (TLSZ = 00) 2-8 (TLSZ = 01) 2-31 (TLSZ = 10) Max Table Size 16K x 72-bit 128K x 72-bit 496K x 72-bit Latency in CLK Cycles 4 5 6 123/159 M7040N DEPTH-CASCADING The search engine application can depth-cascade the device to various table sizes of different widths (e.g., 72-bit, 144-bit, and 288-bit configurations). The devices perform all the necessary arbitration to decide which device drives the SRAM Bus. The latency of the searches increases as the table size increases while the search rate remains constant. Depth-Cascading Up to Eight Devices (One Block) Figure 93, page 125 shows how up to eight devices can cascade to form a 512K x 72, 256K x 144, or 128K x 288 bit table. It also shows the interconnection between the devices for depth-cascading. Each Search Engine asserts the LHO[1] and LHO[0] signals to inform downstream devices of its result. The LHI[6:0] signals for a device are connected to LHO signals of the upstream devices. The host ASIC must program the TLSZ to '01' for each of up to eight devices in a block. Only a single device drives the SRAM Bus in any single cycle. Depth-Cascading Up to 31 Devices (4 Blocks) Figure 94, page 126 shows how to cascade up to four blocks. Each block contains up to eight M7040Ns (except the last block) and the interconnection within each is shown in Figure 93, page 125. Note: The interconnection between blocks for depth-cascading is important. For each SEARCH, a block asserts BHO[2], BHO[1], and BHO[0]. The BHO[2:0] signals for a block are the signals taken only from the last device in the block. For all other devices within that block, these signals stay open and floating. The host ASIC must program the table size (TLSZ) field to '10' in each of the devices for cascading up to 31 devices (in up to four blocks). Depth-Cascading to Generate a "FULL" Signal Bit[0] of each of the 72-bit entries is designated as a special bit (1 = occupied; 0 = empty). For each LEARN or PIO WRITE to the data array, each device asserts FULO[1] and FULO[0] if it does not have any empty locations (see Figure 95, page 127). Each device combines the FULO signals from the devices above it with its own "full" status to generate a FULL signal that gives the "full" status of the table up to the device asserting the FULL signal. Figure 95, page 127 shows the hardware connection diagram for generating the FULL signal that goes back to the ASIC. In a depth-cascaded block of up to eight devices, the FULL signal from the last device should be fed back to the ASIC controller to indicate the fullness of the table. The FULL signal of the other devices should be left open. Note: The LEARN instruction is supported for only up to eight devices, whereas FULL cascading is allowed only for one block in tables containing more than eight devices. In tables for which a LEARn instruction is not going to be used, the Bit[0] of each 72-bit entry should always be set to '1.' 124/159 M7040N Figure 93. Depth-Cascading to Form a Single Block SRAM BHI[2:0] LHO[1] 6 5 4 M7040 #0 3 LHI 2 1 0 LHO[0] SSF, SSV BHI[2:0] LHO[1] M7040 #1 6 5 4 3 LHI 2 1 LHO[0] 0 DQ[71:0] CMDV CMD[10:0] BHI[2:0] LHO[1] 6 5 4 3 2 LHI LHO[0] 1 0 M7040 #2 BHI[2:0] LHO[1] 6 5 4 M7040 #3 3 LHI LHO[0] 2 1 0 BHI[2:0] 6 5 4 M7040 #4 32 LHI 1 0 LHO[0] BHI[2:0] 3 2 1 LHI 0 6 M7040 #5 5 4 LHI LHO[0] BHI[2:0] 3 2 1 LHI 0 6 M7040 #6 5 4 LHI LHO[0] BHI[2:0] 3 2 1 LHI 0 6 M7040 #7 5 LHI 4 BHO[0] BHO[1] BHO[0] BHO[1] BHO[2] BHO[2] LHO[1] LHO[0] AI04679 125/159 M7040N Figure 94. Depth-Cascading Four Blocks BHI[2] BHI[1] BHI[0] GND SSF, SSV BHO[2] Block of 8 M7040s, Block 0 (Devices 0-7) BHO[1] BHO[0] SRAM BHI[2] BHI[1] BHI[0] GND Block of 8 M7040s, Block 1 (Devices 8-15) BHO[2] BHO[1] BHO[0] BHI[2] BHI[1] BHI[0] GND Block of 8 M7040s, Block 2 (Devices 16-23) BHO[2] BHO[1] BHO[0] BHI[2] BHI[1] BHI[0] DQ[71:0] CMD[10:0], CMDV Block of 7 M7040s, Block 3 (Devices 24-30) BHO[2] BHO[1] BHO[0] AI04684 126/159 M7040N Figure 95. "FULL" Generation in a Cascaded Table DQ[71:0] 6 FULO[1] 5 VDDQ 4 3 FULI 2 1 0 M7040 FULO[0] FULL VDDQ FULO[1] M7040 6 5 4 3 FULI 2 1 0 FULO[0] FULL VDDQ 6 FULO[1] 5 M7040 4 3 2 1 FULI FULO[0] 0 FULL VDDQ 6 FULO[1] 5 M7040 4 3 2 FULI FULO[0] 1 0 FULL VDDQ 6 M7040 5 4 3 FULI FULO[0] 2 1 0 FULL VDDQ 3 2 1 FULI 0 6 5 M7040 4 FULI FULL FULO[0] VDDQ 3 2 1 FULI 0 6 5 M7040 4 FULI FULO[0] FULL 3 2 1 FULI 0 6 5 M7040 4 FULI FULL FULO[1] FULO[0] AI04735 127/159 M7040N SRAM ADDRESSING Table 52 describes the commands used to generate addresses on the SRAM Address Bus. The index [15:0] field contains the address of a 72-bit entry that results in a hit in 72-bit-configured quadrant. It is the address of the 72-bit entry that lies at the 144-bit page, and the 288-bit page boundaries in 144-bit- and 288-bit-configured quadrants, respectively. REGISTERS, page 22 of this specification, describes the NFA and SSR Registers. ADR[15:0] contains the address supplied on the DQ Bus during PIO access to the M7040N. Command Bits 8, 7, and 6 {CMD[8:6]} are passed from the command to the SRAM Address Bus (see COMMAND CODES AND PARAMETERS, page 30 for more information). ID[4:0] is the ID of the device driving the SRAM Bus (see Figure 3, page 9 and Table 2, page 8 for more information). Table 52. Generating an SRAM Bus Address Command SEARCH LEARN PIO READ PIO WRITE Indirect Access SRAM Operation READ WRITE READ WRITE WRITE/READ 23 C8 C8 C8 C8 C8 22 C7 C7 C7 C7 C7 21 C6 C6 C6 C6 C6 [20:16] ID[4:0] ID[4:0] ID[4:0] ID[4:0] ID[4:0] [15:0] Index[15:0] NFA[15:0] ADR[15:0] ADR[15:0] SSR[15:0] SRAM PIO Access SRAM READ enables READ access to off-chip SRAM that contains associative data. The latency from the issuance of the READ Instruction to the address appearing on the SRAM Bus is the same as the latency of the SEARCH Instruction and will depend on the TLSZ value parameter programmed in the device Configuration Register. The latency of the ACK from the READ Instruction is the same as the latency of the SEARCH Instruction to the SRAM address plus the HLAT programmed in the Configuration Register. Note: SRAM READ is a blocking operation - no new instruction can begin until the ACK is returned by the selected device performing the access. SRAM WRITE enables WRITE access to the offchip SRAM containing associative data. The latency from the second cycle of the WRITE Instruction to the address appearing on the SRAM Bus is the same as the latency of the SEARCH Instruction and will depend on the TLSZ value parameter programmed in the device Configuration Register. Note: SRAM WRITE is a pipelined operation - new instruction can begin right after the previous command has ended. SRAM READ with a Table of One Device SRAM READ enables READ access to the offchip SRAM containing associative data. The latency from the issuance of the READ Instruction to the address appearing on the SRAM Bus is the same as the latency of the SEARCH Instruction and will depend on the TLSZ value parameter programmed in the device configuration register. The latency of the ACK from the READ Instruction is the same as the latency of the SEARCH Instruction to the SRAM address plus the HLAT programmed in the configuration register. The following explains the SRAM READ operation in a table with only one device that has the following parameters: TLSZ = 00, HLAT = 000, LRAM = 1, and LDEV = 1. Figure 96, page 129 shows the associated timing diagram. For the following description, the selected device refers to the only device in the table because it is the only device to be accessed. The sequence of the operation is as follows: - Cycle 1A: The host ASIC applies the READ Instruction on the CMD[1:0], using CMDV = 1. The DQ Bus supplies the address with DQ[20:19] set to '10' to select the SRAM address. The host ASIC selects the device for which the ID[4:0] matches the DQ[25:21] lines. During this cycle, the host ASIC also supplies SADR[23:21] on CMD[8:6] in this cycle. - Cycle 1B: The host ASIC continues to apply the READ Instruction on the CMD[1:0] using CMDV = 1. The DQ Bus supplies the address with DQ[20:19] set to '10' to select the SRAM address. 128/159 M7040N - Cycle 2: The host ASIC floats DQ[71:0] to a 3state condition. - Cycle 3: The host ASIC keeps DQ[71:0] in a 3state condition. - Cycle 4: The selected device starts to drive DQ[71:0] and drives ACK from High-Z to low. - Cycle 5: The selected device drives the READ address on SADR[23:0]; it also drives ACK high, CE_L low, and ALE_L low. - Cycle 6: The selected device drives CE_L high, ALE_L high, the SADR Bus, and the DQ Bus in a 3-state condition; it drives ACK low. At the end of Cycle 6, the selected device floats ACK in a 3-state condition, and a new command can begin. Figure 96. SRAM READ Access for One Device Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 CLK2X PHS_L CMDV CMD[1:0] READ CMD[10:2] DQ OE_L WE_L CE_L 1 0 1 1 A B z z Address (DQ driven by M7040) 0 0 1 1 ALE_L SADR ACK SSV SSF z 0 0 0 Address z 0 1 HLAT = 000, TLSZ = 00, LRAM = 1, LDEV = 1 AI04736 129/159 M7040N SRAM READ with a Table of Up to Eight Devices The following explains the SRAM READ operation completed through a table of up to eight devices using the following parameters: TLSZ = 01. Figure 97, page 131 diagrams a block of eight devices. The following assumes that SRAM access is successfully achieved through M7040N Device 0. Figure 98, page 132 and Figure 99, page 133 show timing diagrams for Device 0 and Device 7, respectively. - Cycle 1A: The host ASIC applies the READ Instruction on the CMD[1:0] using CMDV = 1. The DQ Bus supplies the address, with DQ[20:19] set to '10' to select the SRAM address. The host ASIC selects the device for which ID[4:0] matches the DQ[25:21] lines. During this cycle the host ASIC also supplies SADR[23:21] on CMD[8:6]. - Cycle 1B: The host ASIC continues to apply the READ Instruction on the CMD[1:0] using CMDV = 1. The DQ Bus supplies the address with DQ[20:19] set to '10' to select the SRAM address. - Cycle 2: The host ASIC floats DQ[71:0] to a 3state condition. - Cycle 3: The host ASIC keeps DQ[71:0] in a 3state condition. - Cycle 4: The selected device starts to drive DQ[71:0]. - Cycle 5: The selected device continues to drive DQ[71:0] and drives ACK from high-Z to low - Cycle 6: The selected device drives the READ address on SADR[23:0]. It also drives ACK high, CE_L low, WE_L high, and ALE_L low. - Cycle 7: The selected device drives CE_L, ALE_L, WE_L, and the DQ Bus in a 3-state condition. It continues to drive ACK low. At the end of Cycle 7, the selected device floats ACK in 3-state condition and a new command can begin. 130/159 M7040N Figure 97. Table with Eight Devices SRAM BHI[2:0] LHO[1] 6 5 4 M7040 #0 3 LHI 2 1 0 LHO[0] SSF, SSV BHI[2:0] LHO[1] M7040 #1 6 5 4 3 LHI 2 1 LHO[0] 0 DQ[71:0] CMDV CMD[10:0] BHI[2:0] LHO[1] 6 5 4 3 2 LHI LHO[0] 1 0 M7040 #2 BHI[2:0] LHO[1] 6 5 4 M7040 #3 3 LHI LHO[0] 2 1 0 BHI[2:0] 6 5 4 M7040 #4 32 LHI 1 0 LHO[0] BHI[2:0] 3 2 1 LHI 0 6 M7040 #5 5 4 LHI LHO[0] BHI[2:0] 3 2 1 LHI 0 6 M7040 #6 5 4 LHI LHO[0] BHI[2:0] 3 2 1 LHI 0 6 M7040 #7 5 LHI 4 BHO[0] BHO[1] BHO[0] BHO[1] BHO[2] BHO[2] LHO[1] LHO[0] AI04679 131/159 M7040N Figure 98. SRAM READ Through Device 0 in a Block of Eight Devices Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 CLK2X PHS_L CMDV CMD[1:0] READ CMD[10:2] DQ OE_L WE_L CE_L ALE_L SADR ACK SSV SSF z z A B z z Address (DQ driven by the selected M7040) 1 0 0 z z z z z z Address z 0 z z 1 0 HLAT = 000, TLSZ = 01, LRAM = 0, LDEV = 0 AI04737 132/159 M7040N Figure 99. SRAM READ Timing for Device 7 in a Block of Eight Devices Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 CLK2X PHS_L CMDV CMD[1:0] READ CMD[10:2] DQ OE_L WE_L CE_L ALE_L SADR ACK SSV SSF z z z 0 A B z Address 1 1 1 z z z z 1 1 1 HLAT = 000, TLSZ = 01, LRAM = 1, LDEV = 1 AI04738 133/159 M7040N SRAM READ with a Table of Up to 31 Devices The following explains the SRAM READ operation accomplished through a table of up to 31 devices, using the following parameters: TLSZ = 10. The diagram of such a table is shown in Figure 100, page 135. The following assumes that SRAM access is being accomplished through M7040N Device 0 and that Device 0 is the selected device. Figure 101, page 136 and Figure 102, page 137 show the timing diagrams for Device 0 and Device 30, respectively. - Cycle 1A: The host ASIC applies the READ Instruction to CMD[1:0] using CMDV = 1. The DQ Bus supplies the address, with DQ[20:19] set to '10,' to select the SRAM address. The host ASIC selects the device for which the ID[4:0] matches the DQ[25:21] lines. During this cycle, the host ASIC also supplies SADR[23:21] on CMD[8:6]. - Cycle 1B: The host ASIC continues to apply the READ Instruction to CMD[1:0] using CMDV = 1. The DQ Bus supplies the address, with DQ[20:19] set to '10,' to select the SRAM address. - Cycle 2: The host ASIC floats DQ[71:0] to a 3state condition. - Cycle 3: The host ASIC keeps DQ[71:0] in a 3state condition. - Cycle 4: The selected device starts to drive DQ[71:0]. - Cycles 5 to 6: The selected device continues to drive DQ[71:0]. - Cycle 7: The selected device continues to drive DQ[71:0] and drives an SRAM READ cycle. - Cycle 8: The selected device drives ACK from Z to low. - Cycle 9: The selected device drives ACK to high. - Cycle 10: The selected device drives ACK from high to low. At the end of Cycle 10, the selected device floats ACK in a 3-state condition. 134/159 M7040N Figure 100. Table of 31 Devices Made of Four Blocks BHI[2] BHI[1] BHI[0] GND SSF, SSV BHO[2] Block of 8 M7040s, Block 0 (Devices 0-7) BHO[1] BHO[0] SRAM BHI[2] BHI[1] BHI[0] GND Block of 8 M7040s, Block 1 (Devices 8-15) BHO[2] BHO[1] BHO[0] BHI[2] BHI[1] BHI[0] GND Block of 8 M7040s, Block 2 (Devices 16-23) BHO[2] BHO[1] BHO[0] BHI[2] BHI[1] BHI[0] DQ[71:0] CMD[10:0], CMDV Block of 7 M7040s, Block 3 (Devices 24-30) BHO[2] BHO[1] BHO[0] AI04684 135/159 M7040N Figure 101. SRAM READ Through Device 0 in a Bank of 31 Devices (Device 0 Timing) Cycle 2 Cycle 4 Cycle 6 Cycle 8 Cycle 10 Cycle 1 Cycle 3 Cycle 5 Cycle 7 Cycle 9 CLK2X PHS_L CMDV READ CMD[1:0] 00 CMD[10:2] A B Address DQ OE_L WE_L CE_L ALE_L SADR[23:0] z z DQ driven by the selected M7040 1 0 z z z z z z 0 Address z ACK SSV SSF z 0 z z 1 z 0 HLAT = 010, TLSZ = 01, LRAM = 0, LDEV = 0 AI04739 136/159 M7040N Figure 102. SRAM READ Through Device 0 in a Bank of 31 Devices (Device 30 Timing) Cycle 2 Cycle 4 Cycle 6 Cycle 8 Cycle 10 Cycle 1 Cycle 3 Cycle 5 Cycle 7 Cycle 9 CLK2X PHS_L CMDV READ CMD[1:0] 00 CMD[10:2] A B Address DQ OE_L WE_L CE_L ALE_L SADR[23:0] ACK SSV SSF z 0 0 0 z z z z 1 1 1 1 1 1 HLAT = 010, TLSZ = 01, LRAM = 1, LDEV = 1 AI04740 137/159 M7040N SRAM WRITE with a Table of One Device SRAM WRITE enables WRITE access to the offchip SRAM that contains associative data. The latency from the second cycle of the WRITE Instruction to the address appearing on the SRAM Bus is the same as the latency of the SEARCH Instruction, and will depend on the TLSZ value parameter programmed in the device configuration register. The following explains the SRAM WRITE operation accomplished with a table of only one device of the following parameters: TLSZ = 00, HLAT = 000, LRAM = 1, and LDEV = 1. Figure 103, page 139 shows the timing diagram. For the following description the selected device refers to the only device in the table as it is the only device that will be accessed. - Cycle 1A: The host ASIC applies the WRITE Instruction on CMD[1:0] using CMDV = 1. The DQ Bus supplies the address with DQ[20:19] set to '10' to select the SRAM address. The host ASIC selects the device for which the ID[4:0] matches the DQ[25:21] lines. The host ASIC also supplies SADR[23:21] on CMD[8:6] in this cycle. Note: CMD[2] must be set to '0' for SRAM WRITE because Burst WRITEs into the SRAM are not supported. - Cycle 1B: The host ASIC continues to apply the WRITE Instruction on CMD[1:0], using CMDV = 1. The DQ Bus supplies the address with DQ[20:19] set to '10' to select the SRAM address. Note: CMD[2] must be set to '0' for SRAM WRITE because Burst WRITEs into the SRAM are not supported. - Cycle 2: The host ASIC continues to drive DQ[71:0]. The data in this cycle is not used by the M7040N device. - Cycle 3: The host ASIC continues to drive DQ[71:0]. The data in this cycle is not used by the M7040N device. At the end of Cycle 3, a new command can begin. The WRITE is a pipelined operation. The WRITE Cycle appears at the SRAM Bus, however, with the same latency as that of a SEARCH Instruction, as measured from the second cycle of the WRITE command. 138/159 M7040N Figure 103. SRAM WRITE Access for One Device Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 CLK2X PHS_L CMDV CMD[1:0] WRITE CMD[10:2] DQ A B Address X X OE_L WE_L CE_L ALE_L SADR ACK SSV SSF 0 1 1 0 1 0 1 0 Address z 0 0 HLAT = 000, TLSZ = 00, LRAM = 1, LDEV = 1 AI04741 139/159 M7040N SRAM WRITE with a Table of Up to Eight Devices The following explains the SRAM WRITE operation done through a table(s) of up to eight devices with the following parameters (TLSZ = 01). The diagram of such a table is shown in Figure 104, page 141. The following assumes that SRAM access is done through M7040N Device 0. Figure 105, page 142 and Figure 106, page 143 show the timing diagram for Device 0 and Device 7, respectively. - Cycle 1A: The host ASIC applies the WRITE Instruction on CMD[1:0] using CMDV = 1. The DQ Bus supplies the address with DQ[20:19] set to '10' to select the SRAM address. The host ASIC selects the device for which the ID[4:0] matches the DQ[25:21] lines. The host ASIC also supplies SADR[23:21] on CMD[8:6] in this cycle. Note: CMD[2] must be set to '0' for SRAM WRITE because Burst WRITEs into the SRAM are not supported. - Cycle 1B: The host ASIC continues to apply the WRITE Instruction on CMD[1:0] using CMDV = 1. The DQ Bus supplies the address with DQ[20:19] set to '10' to select the SRAM address. Note: CMD[2] must be set to '0' for SRAM WRITE because Burst WRITEs into the SRAM are not supported. - Cycle 2: The host ASIC continues to drive DQ[71:0]. The data in this cycle is not used by the M7040N device. - Cycle 3: The host ASIC continues to drive DQ[71:0]. The data in this cycle is not used by the M7040N device. At the end of cycle 3, a new command can begin. The WRITE is a pipelined operation. The WRITE Cycle appears at the SRAM Bus, however, with the same latency as that of a SEARCH Instruction, as measured from the second cycle of the WRITE command. 140/159 M7040N Figure 104. Table with Eight Devices SRAM BHI[2:0] LHO[1] 6 5 4 M7040 #0 3 LHI 2 1 0 LHO[0] SSF, SSV BHI[2:0] LHO[1] M7040 #1 6 5 4 3 LHI 2 1 LHO[0] 0 DQ[71:0] CMDV CMD[10:0] BHI[2:0] LHO[1] 6 5 4 3 2 LHI LHO[0] 1 0 M7040 #2 BHI[2:0] LHO[1] 6 5 4 M7040 #3 3 LHI LHO[0] 2 1 0 BHI[2:0] 6 5 4 M7040 #4 32 LHI 1 0 LHO[0] BHI[2:0] 3 2 1 LHI 0 6 M7040 #5 5 4 LHI LHO[0] BHI[2:0] 3 2 1 LHI 0 6 M7040 #6 5 4 LHI LHO[0] BHI[2:0] 3 2 1 LHI 0 6 M7040 #7 5 LHI 4 BHO[0] BHO[1] BHO[0] BHO[1] BHO[2] BHO[2] LHO[1] LHO[0] AI04679 141/159 M7040N Figure 105. SRAM WRITE Through Device 0 in a Block of Eight Devices Cycle 2 Cycle 4 Cycle 6 Cycle 8 Cycle 10 Cycle 1 Cycle 3 Cycle 5 Cycle 7 Cycle 9 CLK2X PHS_L CMDV WRITE CMD[1:0] 01 CMD[10:2] A B Address DQ OE_L WE_L CE_L ALE_L SADR[23:0] ACK SSV SSF z X X z z 0 z 0 z 0 Address z z z z z z z z HLAT = XXX, TLSZ = 01, LRAM = 0, LDEV = 0 AI04742 142/159 M7040N Figure 106. SRAM WRITE Timing for Device 7 in a Block of Eight Devices Cycle 2 Cycle 4 Cycle 6 Cycle 8 Cycle 10 Cycle 1 Cycle 3 Cycle 5 Cycle 7 Cycle 9 CLK2X PHS_L CMDV WRITE CMD[1:0] 01 CMD[10:2] A B Address DQ OE_L WE_L CE_L ALE_L 0 X X 0 z z z z 1 1 1 1 1 1 1 SADR[23:0] ACK SSV SSF z 0 0 HLAT = XXX, TLSZ = 01, LRAM = 1, LDEV = 1 AI04743 143/159 M7040N SRAM WRITE with Table(s) of Up to 31 Devices The following explains the SRAM WRITE operation done through a table(s) of up to 31 devices with the following parameters (TLSZ = 10). The diagram of such table(s) is shown in Figure 107, page 145. The following assumes that SRAM access is done through M7040N Device 0 - Device 0 is the selected device. Figure 108, page 146 and Figure 109, page 147 show the timing diagram for Device 0 and Device 30, respectively. - Cycle 1A: The host ASIC applies the WRITE Instruction on CMD[1:0] using CMDV = 1. The DQ Bus supplies the address with DQ[20:19] set to '10' to select the SRAM address. The host ASIC selects the device for which the ID[4:0] matches the DQ[25:21] lines. The host ASIC also supplies SADR[23:21] on CMD[8:6] in this cycle. Note: CMD[2] must be set to '0' for SRAM WRITE because Burst WRITEs into the SRAM are not supported. - Cycle 1B: The host ASIC continues to apply the WRITE Instruction on CMD[1:0] using CMDV = 1. The DQ Bus supplies the address with DQ[20:19] set to '10' to select the SRAM address. Note: CMD[2] must be set to '0' for SRAM WRITE because Burst WRITEs into the SRAM are not supported. - Cycle 2: The host ASIC continues to drive DQ[71:0]. The data in this cycle is not used by the M7040N device. - Cycle 3: The host ASIC continues to drive DQ[71:0]. The data in this cycle is not used by the M7040N device. At the end of Cycle 3, a new command can begin. The WRITE is a pipelined operation. The WRITE Cycle appears at the SRAM Bus, however, with the same latency as that of a SEARCH Instruction, as measured from the second cycle of the WRITE command 144/159 M7040N Figure 107. Table of 31 Devices (Four Blocks) BHI[2] BHI[1] BHI[0] GND SSF, SSV BHO[2] Block of 8 M7040s, Block 0 (Devices 0-7) BHO[1] BHO[0] SRAM BHI[2] BHI[1] BHI[0] GND Block of 8 M7040s, Block 1 (Devices 8-15) BHO[2] BHO[1] BHO[0] BHI[2] BHI[1] BHI[0] GND Block of 8 M7040s, Block 2 (Devices 16-23) BHO[2] BHO[1] BHO[0] BHI[2] BHI[1] BHI[0] DQ[71:0] CMD[10:0], CMDV Block of 7 M7040s, Block 3 (Devices 24-30) BHO[2] BHO[1] BHO[0] AI04684 145/159 M7040N Figure 108. SRAM WRITE Through Device 0 in a Bank of 31 Devices (Device 0 Timing) Cycle 2 Cycle 4 Cycle 6 Cycle 8 Cycle 10 Cycle 1 Cycle 3 Cycle 5 Cycle 7 Cycle 9 CLK2X PHS_L CMDV WRITE CMD[1:0] 01 CMD[10:2] A B Address DQ OE_L WE_L z z z X X z z 0 z 0 z 0 Address CE_L z ALE_L SADR[23:0] ACK SSV SSF z z z z z HLAT = XXX, TLSZ = 10, LRAM = 0, LDEV = 0 AI04744 146/159 M7040N Figure 109. SRAM WRITE Through Device 0 in a Bank of 31 Devices (Device 30 Timing) Cycle 2 Cycle 4 Cycle 6 Cycle 8 Cycle 10 Cycle 1 Cycle 3 Cycle 5 Cycle 7 Cycle 9 CLK2X PHS_L CMDV WRITE CMD[1:0] 01 CMD[10:2] A B Address DQ OE_L WE_L CE_L ALE_L 0 X X 1 z z z z 1 1 1 1 1 1 SADR[23:0] ACK SSV SSF z 0 0 HLAT = XXX, TLSZ = 10, LRAM = 1, LDEV = 1 AI04745 147/159 M7040N JTAG (1149.1) TESTING The M7040N supports the Test Access Port and Boundary Scan Architecture as specified in the IEEE JTAG standard 1149.1. The pin interface to the chip consists of five signals with the standard definitions: TCK, TMS, TDI, TDO, and TRST_L. Table 53 describes the operations that the test acTable 53. Supported Operations Instruction SAMPLE/PRELOAD Type Mandatory Description Sample/Preload. Loads the values of signals going to and from IO pins into the boundary scan shift register to provide a snapshot of the normal functional operation. External Test. Uses boundary scan values shifted in from TAP to test connectivity external to the device. Internal Test. Allows slow-speed, functional testing of the device using the boundary scan register to provide the I/O values. cess port controller supports and Table 54 describes the TAP Device ID Register. Note: To disable JTAG functionality, connect the TCK, TMS, and TDI pins to Ground, and TRST_L to VDD. EXTEST INTEST Mandatory Optional Table 54. TAP Device ID Register Field Revision Part # MFID LSB Range [31:28] [27:12] [11:1] [0] Initial Value 0001 0000 0000 0000 0100 000_1101_1100 1 Description Revision Number. This is the current device revision number. Numbers start from one and increment by one for each revision of the device. This is the part number for this device. Manufacturer ID. This field is the same as the manufacturer ID used in the TAP controller. Least Significant Bit 148/159 M7040N PART NUMBERING Table 55. Ordering Information Scheme Example: M70 40 N -100 ZA 1 T Device Type M70 Search Engine Density 40 = 4.5Mb (64K x 72-bit Table Entries) Operating Supply Voltage N = VDD = 1.5V for -066 and -083 speed grades VDD = 1.65V for -100 speed grade Speed -100 = 100 Million Searches per Second -083 = 83 Million Searches per Second -066 = 66 Million Searches per Second Package PBGA = 388-ball count, 35mm x 35mm(1), 1.27mm ball pitch Temperature Range 1 = 0 to 70C Shipping Option Tape & Reel Packing = T Note: 1. Where "Z" is the symbol for BGA packages and "A" denotes 1.27mm ball pitch For a list of available options (e.g., Speed, Package) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you. 149/159 M7040N PACKAGE MECHANICAL INFORMATION Figure 110. PBGA-ZA - 388-ball Plastic Ball Grid Array Package Outline 0.56 REF. A D2 A2 30 TYP. 1.17 REF PIN A1 E2 A 4.00*45 (4x) TOP VIEW ddd C B SIDE VIEW e eee S C A S B S fff S C b E1 E e SOLDER BALL (Typ) 1 DETAIL A PIN 1 CORNER 1 b Detail A e D1 D 0.20 (4X) BOTTOM VIEW PBGA-Z05 Note: Drawing is not to scale. 150/159 M7040N Table 56. PBGA-ZA - 388-ball Plastic Ball Grid Array Package Mechanical Data mm Symb Typ A A2 b(1,2) D(3,4) D1 D2 E(3,4) e E1 E2 n 2.33 0.56 0.75 35.00 31.75 30.00 35.00 1.27 31.75 30.00 388 Tolerance ddd eee fff 0.15 0.30 0.15 34.80 35.20 0.60 34.80 0.90 35.20 Min 2.20 Max 2.46 Typ 0.095 0.022 0.031 1.429 1.296 1.224 1.429 0.050 1.296 1.224 388 Tolerance 0.006 0.012 0.006 1.420 1.437 0.024 1.420 0.037 1.437 Min 0.090 Max 0.100 inches Note: 1. The terminal "b" corner must be identified on the top surface by using a corner chamfer, ink, or metallized markings, or other feature of package body or integral heatslug. 2. A distinguished feature is allowable on the bottom surface of the package to identify the terminal "b" corner. 3. Maximum mounted height is 2.45mm based on a 0.65mm ball pad diameter. Solder paste is 0.15mm thickness and 0.65mm in diameter. 4. Exact shape of each corner is optional. 151/159 M7040N APPENDIX APPENDIX A. DESCRIPTIONS FOR CONNECTION DIAGRAM (FIGURE 3, PAGE 9) Table 57. Connections Package Ball Number A1 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A2 A20 A21 A22 A23 A24 A25 A26 A3 A4 A5 A6 A7 A8 A9 AA1 AA2 AA23 Signal Name CLK_TUNE[3](1) DQ[43] DQ[41] DQ[37] DQ[35] DQ[31] VDDQ(2) DQ[25] DQ[21] DQ[17] VDDQ(2) DQ[71] DQ[09] DQ[05] DQ[03] TEST_FM VDDQ(2) HIGH_SPEED CLK_TUNE[0](1) VDDQ(2) DQ[67] DQ[63] VDDQ(2) DQ[57] DQ[53] DQ[51] FULO[1] VDDQ(2) VSS Signal Type Note 1 I/O I/O I/O I/O I/O 2.5/3.3V I/O I/O I/O 2.5/3.3V I/O I/O I/O I/O Ground 2.5/3.3V Input Note 1 2.5/3.3V I/O I/O 2.5/3.3V I/O I/O I/O Output-T 2.5/3.3V Ground Package Ball Number AA26 AA3 AA4 AB1 AB2 AB23 AB24 AB25 AB26 AB3 AB4 AC1 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC2 AC20 AC21 AC22 AC23 AC24 AC25 Signal Name CMD[2] VDD VSS FULL ACK VSS VDD CMD[5] CMD[4] VDD VSS VSS VSS VDD VDD VDD VDD VDD VDD VSS VSS VSS EOT VSS VSS VSS VSS VDD CMD[6] Signal Type Input 1.5V Ground Output-T Output-T Ground 1.5V Input Input 1.5V Ground Ground Ground 1.5V 1.5V 1.5V 1.5V 1.5V 1.5V Ground Ground Ground Output-T Ground Ground Ground Ground 1.5V Input 152/159 M7040N Package Ball Number AA24 AA25 AC4 AC5 AC6 AC7 AC8 AC9 AD1 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD2 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD3 AD4 AD5 AD6 AD7 AD8 AD9 Package Ball Number AC26 AC3 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE2 AE20 AE21 AE22 AE23 AE24 AE25 AE26 AE3 AE4 AE5 AE6 AE7 AE8 AE9 AF1 AF10 AF11 AF12 AF13 AF14 AF15 Signal Name VDD CMD[3] VSS VSS VSS VSS VSS VSS RST_L DQ[46] VDD VDD VDD VDD VDD VDD DQ[20] DQ[16] NC4 VDDQ(2) VDD VDD VDD VDD VDD CMD[8] CMD[7] VDD VDD VDD VDD VDD NC3 VDDQ(2) Signal Type 1.5V Input Ground Ground Ground Ground Ground Ground Input I/O 1.5V 1.5V 1.5V 1.5V 1.5V 1.5V I/O I/O No Connect 2.5/3.3V 1.5V 1.5V 1.5V 1.5V 1.5V Input Input 1.5V 1.5V 1.5 V 1.5V 1.5V No Connect 2.5/3.3V Signal Name VDDQ(2) VDD DQ[44] DQ[42] DQ[38] VDDQ(2) DQ[32] DQ[28] DQ[26] VDDQ(2) DQ[18] DQ[12] VSS DQ[10] DQ[06] VDDQ(2) DQ[00] VDDQ(2) VSS CLK_TUNE[1](1) DQ[70] VDDQ(2) DQ[64] DQ[60] DQ[58] DQ[54] DQ[50] TEST_CO VDDQ(2) DQ[40] DQ[36] DQ[34] DQ[30] VDDQ(2) Signal Type 2.5/3.3V 1.5V I/O I/O I/O 2.5/3.3V I/O I/O I/O 2.5/3.3V I/O I/O Ground I/O I/O 2.5/3.3V I/O 2.5/3.3V Ground Note 1 I/O 2.5/3.3V I/O I/O I/O I/O I/O No Connect 2.5/3.3V I/O I/O I/O I/O 2.5/3.3V 153/159 M7040N Package Ball Number AE1 AF17 AF18 AF19 AF2 AF20 AF21 AF22 AF23 AF24 AF25 AF26 AF3 AF4 AF5 AF6 AF7 AF8 AF9 B1 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B2 B20 B21 B22 Package Ball Number AF16 B23 B24 B25 B26 B3 B4 B5 B6 B7 B8 B9 C1 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C2 C20 C21 C22 C23 C24 C25 C26 C3 C4 C5 Signal Name TEST DQ[22] DQ[14] VDDQ(2) CLK_TUNE[2](1) DQ[08] DQ[04] DQ[02] SSV SSF CMD[10] CMD[9] DQ[68] DQ[66] DQ[62] VDDQ(2) DQ[56] DQ[52] DQ[48] TDI DQ[45] DQ[39] VDDQ(2) DQ[33] DQ[29] DQ[27] DQ[23] VDDQ(2) DQ[15] DQ[11] VSS DQ[07] VDDQ (2) Signal Type Ground I/O I/O 2.5/3.3V Note 1 I/O I/O I/O Output-T Output-T Input Input I/O I/O I/O 2.5/3.3V I/O I/O I/O Input I/O I/O 2.5/3.3V I/O I/O I/O I/O 2.5/3.3V I/O I/O Ground I/O 2.5/3.3V I/O Signal Name DQ[24] TEST_PB CFG_L VSS SADR[00] DQ[69] DQ[65] DQ[61] DQ[59] DQ[55] VDDQ(2) DQ[47] TCK VDDQ(2) VDD VDD VDD VDD VDD VDD DQ[19] DQ[13] NC7 TMS VDD VDD VDD VDD VDD SADR[01] VDDQ(2) VDD VDD VDD Signal Type I/O Input Input Ground Output I/O I/O I/O I/O I/O 2.5/3.3V I/O Input 2.5/3.3V 1.5V 1.5V 1.5V 1.5V 1.5V 1.5V I/O I/O No Connect Input 1.5V 1.5V 1.5V 1.5V 1.5V Output 2.5/3.3V 1.5V 1.5V 1.5V DQ[01] 154/159 M7040N Package Ball Number C6 C7 C8 C9 D1 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D2 D20 D21 D22 D23 D24 D25 D26 D3 D4 D5 D6 D7 D8 D9 E1 E2 E23 J25 Package Ball Number E24 E25 E26 E3 E4 F1 F2 F23 F24 F25 F26 F3 F4 G1 G2 G23 G24 G25 G26 G3 G4 H1 H2 H23 H24 H25 H26 H3 H4 J1 J2 J23 J24 M2 Signal Name VDD VDD NC8 DQ[49] TRST_L VSS VDD VDD VDD VDD VDD VDD VSS VSS VSS TDO VSS VSS VSS VSS VDD SADR[03] SADR[02] VDD VSS VSS VSS VSS VSS VSS ID[0] VDDQ (2) Signal Type 1.5V 1.5V No Connect I/O Input Ground 1.5V 1.5V 1.5V 1.5V 1.5V 1.5V Ground Ground Ground Output-T Ground Ground Ground Ground 1.5V Output Output 1.5V Ground Ground Ground Ground Ground Ground Input 2.5/3.3V Ground Output Signal Name VDD SADR[05] SADR[04] VDD VSS ID[1] ID[2] VSS VDD SADR[06] VDDQ(2) VDD VSS ID[3] ID[4] VSS VDD SADR[08] SADR[07] VDD VSS LHI[0] LHI[1] VSS NC6 VDDQ(2) SADR[09] NC1 VSS LHI[2] LHI[3] VSS SADR[11] BHI[0] Signal Type 1.5V Output Output 1.5V Ground Input Input Ground 1.5V Output 2.5/3.3V 1.5V Ground Input Input Ground 1.5V Output Output 1.5V Ground Input Input Ground No Connect 2.5/3.3V Output No Connect Ground Input Input Ground Output Input VSS SADR[12] 155/159 M7040N Package Ball Number J26 J3 J4 K1 K2 K23 K24 K25 K26 K3 K4 L1 L11 L12 L13 L14 L15 L16 L2 L23 L24 L25 L26 L3 L4 M1 M11 M12 M13 M14 M15 M16 P3 P4 Package Ball Number M23 M24 M25 M26 M3 M4 N1 N11 N12 N13 N14 N15 N16 N2 N23 N24 N25 N26 N3 N4 P1 P11 P12 P13 P14 P15 P16 P2 P23 P24 P25 P26 U24 U25 Signal Name SADR[10] VDDQ (2) Signal Type Output 2.5/3.3V Ground Input Input Ground Output 2.5/3.3V Output Input Ground Output-T Ground Ground Ground Ground Ground Ground Output-T 1.5V 1.5V Output Output 1.5V 1.5V 2.5/3.3V Ground Ground Ground Ground Ground Ground 1.5V 1.5V Signal Name VDD VDD VDDQ(2) SADR[17] VDD VDD BHI[1] VSS VSS VSS VSS VSS VSS BHI[2] VDD VDD SADR[19] SADR[18] VDD VDD BHO[0] VSS VSS VSS VSS VSS VSS MULTI_HIT VDD VDD SADR[21] SADR[20] OE_L PHS_L Signal Type 1.5V 1.5V 2.5/3.3V Output 1.5V 1.5V Input Ground Ground Ground Ground Ground Ground Input 1.5V 1.5V Output Output 1.5V 1.5V Output-T Ground Ground Ground Ground Ground Ground Output-T 1.5V 1.5V Output Output Output-T Input VSS LHI[6] LHI[4] VSS SADR[13] VDDQ(2) SADR[14] LHI[5] VSS LHO[0] VSS VSS VSS VSS VSS VSS LHO[1] VDD VDD SADR[15] SADR[16] VDD VDD VDDQ(2) VSS VSS VSS VSS VSS VSS VDD VDD 156/159 M7040N Package Ball Number R1 R11 R12 R13 R14 R15 R16 R2 R23 R24 R25 R26 R3 R4 T1 T11 T12 T13 T14 T15 T16 T2 T23 T24 T25 T26 T3 T4 U1 U2 U23 Package Ball Number U26 U3 U4 V1 V2 V23 V24 V25 V26 V3 V4 W1 W2 W23 W24 W25 W26 W3 W4 Y1 Y2 Y23 Y24 Y25 Y26 Y3 Y4 Signal Name VDDQ(2) VSS VSS VSS VSS VSS VSS BHO[1] VDD VDD SADR[22] VDDQ(2) VDD VDD BHO[2] VSS VSS VSS VSS VSS VSS VSS VDD VDD CLK_MODE SADR[23] VDD VDD FULI[0] VDDQ(2) VSS Signal Type 2.5/3.3V Ground Ground Ground Ground Ground Ground Output-T 1.5V 1.5V Output 2.5/3.3V 1.5V 1.5V Output-T Ground Ground Ground Ground Ground Ground Ground 1.5V 1.5V Input Output 1.5V 1.5V Input 2.5/3.3V Ground Signal Name CLK1X/CLK2X FULI[1] VSS FULI[2] FULI[3] VSS CE_L VDDQ(2) WE_L FULI[4] VSS VDDQ(2) FULI[5] VSS NC5 CMDV ALE_L NC2 VSS FULI[6] FULO[0] VSS VDD CMD[1] CMD[0] VDD VSS Signal Type Input Input Ground Input Input Ground Output-T 2.5/3.3V Output-T Input Ground 2.5/3.3V Input Ground No Connect Input Output-T No Connect Ground Input Output-T Ground 1.5V Input Input 1.5V Ground Note: 1. CLK_TUNE[3:0] should be programmed to 100%. 2. All VDDQ pins should be set to 2.5 or 3.3V. 157/159 M7040N REVISION HISTORY Table 58. Document Revision History Date April 2001 07/23/01 10/16/01 10/29/01 04/03/02 4/19/02 05/10/02 First Issue Routine maintenance (based on recent data sheet review findings) Addition of 1.8V data Document promoted to "Preliminary Data;" VDDQ corrected (Table 4) Updates per engineering (Figure 3); (Table 1, 2, 3, 4, 6, 8, 55) Improve Mechanical, Connection drawings (Figures 3, 110); change Register Overview (Table 9) Modify Timing Diagrams (Figure 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 91, 99, 103) Revision Details 158/159 M7040N Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners. (c) 2002 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. www.st.com 159/159 |
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